# MT53E1G32D2FW\-046 WT:C (Component)

## Description

This data sheet is for LPDDR4X and LPDDR4 unified product based on LPDDR4X information\. As for LPDDR4 setting, refer to General LPDDR4 Specification at the end of this data sheet\.  Ultra\-low\-voltage core and I/O power supplies  VDD1 = 1\.701\.95V; 1\.80V nominal  VDD2 = 1\.061\.17V; 1\.10V nominal  VDDQ = 0\.570\.65V; 0\.60V nominal or VDDQ = 1\.061\.17V; 1\.10V nominal  Frequency range  213310 MHz \(data rate range per pin: 426620 Mb/s\)  16n prefetch DDR architecture  8 internal banks per cha

## Component Details

- **Owner:** silicon\-yard
- **Created:** 8/17/2026
- **Last Updated:** 8/17/2026
- **Visibility:** Public
- **Manufacturer Part Number:** MT53E1G32D2FW\-046 WT:C
- **Manufacturer Name:** Micron
- **Symbol Style:** parametric\-v1
- **Package or Case Code:** TO
- **Part Type:** Integrated Circuit
- **Mount:** Base
- **Datasheet URL:** https://storage\.googleapis\.com/graviton\-electric\-symbols/document\_assets/user\-uploaded/46017d841a5239bdd4e03fabff048f082d96d16ff108250082a44f2aa62f20a4\.pdf

## Distributor Pricing (qty 1)

*Pricing shown for quantity 1. For price breaks and other quantities, open in Flux.*

| Distributor | Unit Price (qty 1) | Stock |
|------------|--------------------|-------|
| [Digi\-Key](https://www.digikey.com/en/products/detail/micron-technology-inc/MT53E1G32D2FW-046-WT-C/22040994) | N/A | N/A |
| [Mouser](https://www.mouser.com/en/ProductDetail/Micron/MT53E1G32D2FW-046-WTC?qs=Y0Uzf4wQF3l9kYHEIg3mew%253D%253D) | N/A | N/A |

- **Part Type:** Integrated Circuits
- **Sub-Type:** Logic
- **Manufacturer:** Micron
- **MPN:** MT53E1G32D2FW\-046 WT:C
- **Mount Type:** Base
- **Package / Case Code:** TO
- **Pin Count:** 200
- **Logic Function:** AND
## Pins

| Pin | Name | Type |
|-----|------|------|
| F1 | VDD1\_1 |  |
| F12 | VDD1\_2 |  |
| G4 | VDD1\_3 |  |
| G9 | VDD1\_4 |  |
| T4 | VDD1\_5 |  |
| T9 | VDD1\_6 |  |
| U1 | VDD1\_7 |  |
| U12 | VDD1\_8 |  |
| A4 | VDD2\_1 |  |
| A9 | VDD2\_2 |  |
| F5 | VDD2\_3 |  |
| F8 | VDD2\_4 |  |
| H1 | VDD2\_5 |  |
| H5 | VDD2\_6 |  |
| H8 | VDD2\_7 |  |
| H12 | VDD2\_8 |  |
| K1 | VDD2\_9 |  |
| K3 | VDD2\_10 |  |
| K10 | VDD2\_11 |  |
| K12 | VDD2\_12 |  |
| N1 | VDD2\_13 |  |
| N3 | VDD2\_14 |  |
| N10 | VDD2\_15 |  |
| N12 | VDD2\_16 |  |
| R1 | VDD2\_17 |  |
| R5 | VDD2\_18 |  |
| R8 | VDD2\_19 |  |
| R12 | VDD2\_20 |  |
| U5 | VDD2\_21 |  |
| U8 | VDD2\_22 |  |
| AB4 | VDD2\_23 |  |
| AB9 | VDD2\_24 |  |
| B3 | VDDQ\_1 |  |
| B5 | VDDQ\_2 |  |
| B8 | VDDQ\_3 |  |
| B10 | VDDQ\_4 |  |
| D1 | VDDQ\_5 |  |
| D5 | VDDQ\_6 |  |
| D8 | VDDQ\_7 |  |
| D12 | VDDQ\_8 |  |
| F3 | VDDQ\_9 |  |
| F10 | VDDQ\_10 |  |
| U3 | VDDQ\_11 |  |
| U10 | VDDQ\_12 |  |
| W1 | VDDQ\_13 |  |
| W5 | VDDQ\_14 |  |
| W8 | VDDQ\_15 |  |
| W12 | VDDQ\_16 |  |
| AA3 | VDDQ\_17 |  |
| AA5 | VDDQ\_18 |  |
| AA8 | VDDQ\_19 |  |
| AA10 | VDDQ\_20 |  |
| H2 | CA0\_A |  |
| J2 | CA1\_A |  |
| H9 | CA2\_A |  |
| H10 | CA3\_A |  |
| H11 | CA4\_A |  |
| J8 | CK\_T\_A |  |
| J9 | CK\_C\_A |  |
| J11 | CA5\_A |  |
| J4 | CKE0\_A |  |
| J5 | CKE1\_A |  |
| H4 | CS0\_A |  |
| H3 | CS1\_A |  |
| G2 | ODT\_CA\_A |  |
| B2 | DQ0\_A |  |
| C2 | DQ1\_A |  |
| E2 | DQ2\_A |  |
| F2 | DQ3\_A |  |
| F4 | DQ4\_A |  |
| E4 | DQ5\_A |  |
| C4 | DQ6\_A |  |
| B4 | DQ7\_A |  |
| D3 | DQS0\_T\_A |  |
| E3 | DQS0\_C\_A |  |
| C3 | DMI0\_A |  |
| B11 | DQ8\_A |  |
| C11 | DQ9\_A |  |
| E11 | DQ10\_A |  |
| F11 | DQ11\_A |  |
| F9 | DQ12\_A |  |
| E9 | DQ13\_A |  |
| C9 | DQ14\_A |  |
| B9 | DQ15\_A |  |
| D10 | DQS1\_T\_A |  |
| E10 | DQS1\_C\_A |  |
| C10 | DMI1\_A |  |
| R2 | CA0\_B |  |
| P2 | CA1\_B |  |
| R9 | CA2\_B |  |
| R10 | CA3\_B |  |
| R11 | CA4\_B |  |
| P8 | CK\_T\_B |  |
| P9 | CK\_C\_B |  |
| P11 | CA5\_B |  |
| P4 | CKE0\_B |  |
| P5 | CKE1\_B |  |
| R4 | CS0\_B |  |
| R3 | CS1\_B |  |
| T2 | ODT\_CA\_B |  |
| AA2 | DQ0\_B |  |
| Y2 | DQ1\_B |  |
| V2 | DQ2\_B |  |
| U2 | DQ3\_B |  |
| U4 | DQ4\_B |  |
| V4 | DQ5\_B |  |
| Y4 | DQ6\_B |  |
| AA4 | DQ7\_B |  |
| W3 | DQS0\_T\_B |  |
| V3 | DQS0\_C\_B |  |
| Y3 | DMI0\_B |  |
| AA11 | DQ8\_B |  |
| Y11 | DQ9\_B |  |
| V11 | DQ10\_B |  |
| U11 | DQ11\_B |  |
| U9 | DQ12\_B |  |
| V9 | DQ13\_B |  |
| Y9 | DQ14\_B |  |
| AA9 | DQ15\_B |  |
| W10 | DQS1\_T\_B |  |
| V10 | DQS1\_C\_B |  |
| Y10 | DMI1\_B |  |
| T11 | RESET\_N |  |
| A5 | ZQ0 |  |
| A8 | ZQ1 |  |
| A1 | DNU\_1 |  |
| A2 | DNU\_2 |  |
| A11 | DNU\_3 |  |
| A12 | DNU\_4 |  |
| B1 | DNU\_5 |  |
| B12 | DNU\_6 |  |
| AA1 | DNU\_7 |  |
| AA12 | DNU\_8 |  |
| AB1 | DNU\_9 |  |
| AB2 | DNU\_10 |  |
| AB11 | DNU\_11 |  |
| AB12 | DNU\_12 |  |
| G11 | NC\_1 |  |
| K5 | NC\_2 |  |
| K8 | NC\_3 |  |
| N5 | NC\_4 |  |
| N8 | NC\_5 |  |
| A3 | VSS\_1 |  |
| A10 | VSS\_2 |  |
| C1 | VSS\_3 |  |
| C5 | VSS\_4 |  |
| C8 | VSS\_5 |  |
| C12 | VSS\_6 |  |
| D2 | VSS\_7 |  |
| D4 | VSS\_8 |  |
| D9 | VSS\_9 |  |
| D11 | VSS\_10 |  |
| E1 | VSS\_11 |  |
| E5 | VSS\_12 |  |
| E8 | VSS\_13 |  |
| E12 | VSS\_14 |  |
| G1 | VSS\_15 |  |
| G3 | VSS\_16 |  |
| G5 | VSS\_17 |  |
| G8 | VSS\_18 |  |
| G10 | VSS\_19 |  |
| G12 | VSS\_20 |  |
| J1 | VSS\_21 |  |
| J3 | VSS\_22 |  |
| J10 | VSS\_23 |  |
| J12 | VSS\_24 |  |
| K2 | VSS\_25 |  |
| K4 | VSS\_26 |  |
| K9 | VSS\_27 |  |
| K11 | VSS\_28 |  |
| N2 | VSS\_29 |  |
| N4 | VSS\_30 |  |
| N9 | VSS\_31 |  |
| N11 | VSS\_32 |  |
| P1 | VSS\_33 |  |
| P3 | VSS\_34 |  |
| P10 | VSS\_35 |  |
| P12 | VSS\_36 |  |
| T1 | VSS\_37 |  |
| T3 | VSS\_38 |  |
| T5 | VSS\_39 |  |
| T8 | VSS\_40 |  |
| T10 | VSS\_41 |  |
| T12 | VSS\_42 |  |
| V1 | VSS\_43 |  |
| V5 | VSS\_44 |  |
| V8 | VSS\_45 |  |
| V12 | VSS\_46 |  |
| W2 | VSS\_47 |  |
| W4 | VSS\_48 |  |
| W9 | VSS\_49 |  |
| W11 | VSS\_50 |  |
| Y1 | VSS\_51 |  |
| Y5 | VSS\_52 |  |
| Y8 | VSS\_53 |  |
| Y12 | VSS\_54 |  |
| AB3 | VSS\_55 |  |
| AB5 | VSS\_56 |  |
| AB8 | VSS\_57 |  |
| AB10 | VSS\_58 |  |

---

*Generated from [https://flux\.ai/silicon\-yard/mt53e1g32d2fw\-046\-wtc](https://flux.ai/silicon-yard/mt53e1g32d2fw-046-wtc)*