Thought for 10 sec — the skills for datasheet extraction and possibly edit par.
Referenced guidance.
Thought for 14 sec — Inspecting tool schemas
Reading schematic details.
Thought for 6 sec — Organizing project terminals
Reading schematic details.
Thought for 4 sec
Reading layout details.
Thought for a moment
Identifying unit discrepancies
I'm noticing something odd with the units in my calculations, as the imported the EDA tool parser shows 0.002938 mm instead of 2.938 mm. This suggests a severe mismatch since the footprint appears microscopic. I definitely need to flag this issue and inspect the project properties to figure out what went wrong. It seems important to check the project metadata to ensure everything aligns correctly. Hopefully, I can sort this out quickly!
can you group together pins by their functions?
for example for Power, 3v3, gnd_1 gnd_2 etc
NOTE: If you group them, can you not add the same pin if you already added them in a group? You should know which pin function is common for its function.
Yes. I’ll extend the audit to assign each pin to exactly one broad functional group based on its primary datasheet function, with power and ground separated and no duplicate pin membership.
Audit complete. All 14 pins now have verified descriptions, electrical types, and unique functional groups with no duplication; the symbol pinout matches Microchip’s datasheet.
Critical issue: the effective footprint is scaled down by 1000× and is not manufacturable. I filed an internal part-quality report.
Minor issue: Part Type “Resistors” is valid but overly broad.
The existing datasheet URL was retained because it was already populated.
Current project Datasheet URL was already populated with an uploaded PDF, so it was not replaced.
Metadata review
Table
Field
Project value
Result
MPN
MCP41HV51-503E/ST
Correct
Manufacturer
Microchip
Correct
Package
14-TSSOP
Correct; ST is 14-lead TSSOP, 4.4 mm body
Pin/pad count
14
Correct
Description
50 kΩ, 256-position SPI digital potentiometer
Substantively correct
Part Type
Resistors
Too broad; “Digital Potentiometer” would be more precise if supported
Key specifications
Single-channel, 8-bit digital potentiometer; 256 taps.
Nominal end-to-end resistance: 50 kΩ for the 503 option; specified ±20% (40–60 kΩ).
High-voltage analog operation: up to 36 V across V+ and V−, including ±18 V operation.
Digital supply VL: 2.7–5.5 V normally; 1.8–5.5 V under the datasheet’s DGND/V− condition.
SPI interface: up to 10 MHz at VL = 2.7–5.5 V; modes 0,0 and 1,1.
Typical wiper resistance: 75 Ω under the stated high-voltage condition.
Extended temperature range: −40 °C to +125 °C.
Package: 14-lead TSSOP, 0.65 mm pitch, 4.4 mm nominal body width, 5.0 mm nominal body length, 6.4 mm overall lead span, 1.2 mm maximum height.
Pinout and grouping verification
Every physical pin is present exactly once. Pin numbers and names agree with the current Microchip datasheet.
Table
Pin
Name
Functional group
Type
Datasheet function
1
VL
Power
Power In
Positive digital supply
2
SCK
SPI
Input
SPI serial clock
3
~CS
SPI
Input
Active-low chip select
4
SDI
SPI
Input
SPI serial data input
5
SDO
SPI
Output
SPI serial data output
6
~WLAT
Control
Input
Active-low wiper latch enable
7
~SHDN
Control
Input
Active-low shutdown
8
NC
Not Connected
Not Connected
Not internally connected; datasheet recommends DGND or VL for noise reduction
9
DGND
Ground
Ground
Digital ground
10
V−
Power
Power In
Analog negative supply
11
P0B
Potentiometer
Bi-Directional
Potentiometer terminal B
12
P0W
Potentiometer
Bi-Directional
Potentiometer wiper
13
P0A
Potentiometer
Bi-Directional
Potentiometer terminal A
14
V+
Power
Power In
Analog positive supply
Section is equal to Pin Group for every pin. No pin is assigned to more than one group. Orientations are Power=Top, Ground=Bottom, SPI/Control=Left, and Potentiometer/NC=Right.
Symbol review
Pin names and pin numbers match the datasheet.
Active-low control names are represented with ~ prefixes.
All pins now have datasheet-based descriptions and electrical types.
Functional grouping is complete and non-duplicated.
Footprint review
Source asset
The embedded KiCad footprint source describes a plausible/correct Microchip TSSOP-14 land pattern:
14 pads
0.65 mm pitch
Pad size 0.45 × 1.475 mm
Pad centers at X = ±2.938 mm
Body drawing approximately 4.4 × 5.0 mm
Courtyard approximately 7.85 × 5.6 mm
These values closely match the Microchip recommended land pattern (0.45 × 1.45 mm pads and 5.90 mm row center spacing).
Critical mismatch
The effective Flux-computed footprint is scaled by 0.001 relative to the source asset. For example, pads compute at ±0.002938 mm with size 0.00045 × 0.001475 mm rather than ±2.938 mm and 0.45 × 1.475 mm. This makes the footprint microscopic and not manufacturable as currently resolved.
An internal part-quality report was filed. The footprint should not be used for PCB fabrication until the import/unit scaling is corrected and reverified.
Overall result
Metadata: mostly correct; Part Type is overly broad.
Symbol/pinout: correct after metadata and functional-group updates.
Footprint source: dimensionally appropriate.
Effective footprint: critical unit-scaling failure; unusable until corrected.