# LT7911D (Component)

## Description

\-40℃\~\+85℃ 1\.2V、3\.3V 5\.4Gbps Driver I2C QFN\-64\(7\.5x7\.5\) Video Interface ICs ROHS

The LT7911D is a high performance Type\-C to
MIPI®DSI/CSI chip for VR/Display application\.
For DP1\.2 input, LT7911D can be configured as 1/2/4
lane\. Adaptive equalization makes it suitable for long
cable application and the maximum bandwidth is up to
21\.6Gbps\.
For MIPI®DSI/CSI output, LT7911D features
configurable single\-port or dual\-port MIPI®DSI/CSI with
1 high\-speed clock lane and 1\~4 high\-speed data lanes
operating at maximum 1\.5Gbps/lane, which can support
a total bandwidth of up to 12Gbps\. LT7911D supports
burst mode DSI video data transferring, also supports
flexible video data mapping path\. For LVDS output,
LT7911D can be configured as single\-port or dual\-port

Features
 Type\-C
 Compliant with VESA DisplayPort Alt Mode on USB
Type\-C Standard version1\.0
 Compliant with USB Power Delivery Rev\.2\.0
 Compatible with USB Type\-C V1\.1
 Built\-in CC controller for plug and orientation detection
 One port CC for UFP communication
 DP/eDP Receiver
 Compliant with DisplayPort Specification 1\.2 for
1\.62Gbps, 2\.7Gbps ,5\.4Gbps
 Compliant with Embedded DisplayPort \(eDP\)
Specification version 1\.4
 Support DisplayPort 1, 2，4 lanes
 Support HDCP 1\.3
 Support eDP Authentication: Alternative Scramble
Seed Reset
 Adaptive DisplayPort Receiver Equalization for PCB,
cable and connector losses
 Single/Dual\-Port MIPI® DSI/CSI Transmitter
 Compliant with DCS1\.02, D\-PHY1\.2& DSI1\.02
&CSI\-2 1\.0
 1 Clock Lane, and 1\~4 Configurable Data Lanes per
port
 1/2 configurable port
 80Mbps\~1\.5Gbps per data lane
 Maximum 64pixels overlap for each half
 Both non\-burst and burst video mode supported
 Support RGB666, Loosely RGB666, RGB888,
RGB565, 16\-bit YCbCr4:2:2,20\-bit
YCbCr4:2:2,24\-bit YCbCr 4:2:2 Video Format
 Video stream copy mode for each port
 Side\-by\-side 3D support 

 Single/Dual\-Port LVDS Transmitter
 Compatible with VESA and JEIDA standard
 1/2 Configurable Port
 1 clock lane and 4 configurable data lanes per port
 Support Maximum Data Rate 1\.2Gbps/lane
 Output Color Depth supports 6\-bit and 8\-bit
 Video stream copy mode for each port
 Side\-by\-side 3D support
 Miscellaneous
 3\.3V/1\.2V Supply Power
 Internal CSC support conversions between YCbCr
4:4:4 and RGB, and between YCbCr 4:2:2 and YCbCr
4:4:4
 Support SPDIF and 2\-channel IIS audio output
 Support 100KHz I2C slave
 Integrated Microprocessor
 Temperature Range: \-40°C \~ \+85°C
 ESD ±2kV HBM 

\#LT7911D \#Lontium \#DisplayBridge \#DisplayPort \#USBTypeC \#MIPIDSI \#MIPICSI \#LVDS \#VideoConverter \#EmbeddedSystems \#DisplayInterface \#VR \#IndustrialDisplay \#DisplayController

## Component Details

- **Owner:** silicon\-yard
- **Created:** 6/29/2026
- **Last Updated:** 6/29/2026
- **Visibility:** Public
- **Manufacturer Name:** LONTIUM SEMICONDUCTOR
- **Symbol Style:** parametric\-v1
- **License:** https://creativecommons\.org/licenses/by/4\.0/
- **Manufacturer Part Number:** LT7911D
- **Datasheet URL:** https://datasheet4u\.com/download/1556810/LT7911D\.html
- **Part Type:** Integrated Circuits
- **Used in:** 2 projects

- **Part Type:** Integrated Circuits
- **Sub-Type:** Logic
- **MPN:** LT7911D
- **Mount Type:** Standard
- **Package / Case Code:** 16\-QFN
- **Pin Count:** 65
- **Logic Function:** AND
- **Compliance:** Rohs
## Pins

| Pin | Name | Type |
|-----|------|------|
| 1 | VCC12D\_RX |  |
| 2 | D0P |  |
| 3 | D0N |  |
| 4 | VCC12A\_RX |  |
| 5 | D1P |  |
| 6 | D1N |  |
| 7 | VCC33\_RX |  |
| 8 | D2P |  |
| 9 | D2N |  |
| 10 | VCC12\_PI |  |
| 11 | D3P |  |
| 12 | D3N |  |
| 13 | VCC12\_RXPLL |  |
| 14 | UCC1 |  |
| 15 | UCC2 |  |
| 16 | VCC33\_IO |  |
| 17 | AUXP |  |
| 18 | AUXN |  |
| 19 | SLEEP\_33 |  |
| 20 | RST\_N |  |
| 21 | PA28 |  |
| 22 | CSDA |  |
| 23 | RX\_HPD |  |
| 24 | VDD |  |
| 25 | VCC33\_IO |  |
| 26 | GPIO5 |  |
| 27 | IIS\_WS |  |
| 28 | IIS\_SCLK |  |
| 29 | IIS\_MCLK |  |
| 30 | VDD |  |
| 31 | VDDIO\_3 |  |
| 32 | IIS\_D0 |  |
| 33 | VCC33\_TX3 |  |
| 34 | VCC12\_TX3 |  |
| 35 | M0\_L3\_P3 |  |
| 36 | M0\_L3\_N3 |  |
| 37 | M1\_LCK\_P3 |  |
| 38 | M1\_LCK\_N3 |  |
| 39 | MCK\_L2\_P3 |  |
| 40 | MCK\_L2\_N3 |  |
| 41 | M2\_L1\_P3 |  |
| 42 | M2\_L1\_N3 |  |
| 43 | M3\_L0\_P3 |  |
| 44 | M3\_L0\_N3 |  |
| 45 | VCC33\_TX2 |  |
| 46 | VCC12\_TX2 |  |
| 47 | VCC33\_TXPLL |  |
| 48 | VCC12\_TX1 |  |
| 49 | M0\_L3\_P1 |  |
| 50 | M0\_L3\_N1 |  |
| 51 | M1\_LCK\_P1 |  |
| 52 | M1\_LCK\_N1 |  |
| 53 | MCK\_L2\_P1 |  |
| 54 | MCK\_L2\_N1 |  |
| 55 | PB7 |  |
| 56 | PA25 |  |
| 57 | M3\_L0\_P1 |  |
| 58 | M3\_L0\_N1 |  |
| 59 | VCC12\_TX0 |  |
| 60 | PB9/XIN |  |
| 61 | REXT |  |
| 62 | VCC33\_BG |  |
| 63 | XTALO |  |
| 64 | VDDIO\_5 |  |
| 65 | EP |  |

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*Generated from [https://flux\.ai/silicon\-yard/lt7911d](https://flux.ai/silicon-yard/lt7911d)*