Part Datasheet Review

C

cherepanyadima

Check this schematic component against the datasheet for [MPN] and assign the correct pin orientation, section, and terminal order without changing, replacing, renumbering, or remapping any pins. Place Power pins first and Ground pins last. Within each section, distribute the pins between the left and right sides as evenly as possible; for example, split 10 pins as 5/5 and 11 pins as 5/6 or 6/5. If a section contains only one pin, leave it on one side as appropriate. Keep the symbol compact and balanced. If a pin function is unclear, assign Unclear / Check datasheet, then apply all changes directly to the schematic component.

flux

I’ll re-check the JMS578-QGBA0A datasheet pin table, inspect the current terminal properties, then update only pin orientation, section, and terminal order while preserving every existing pin number/name mapping.

flux

I’ve grouped the pins by datasheet function, with Power first, signal sections balanced left/right, No Connect before Ground, and Ground last; applying those terminal-property updates now.

flux

Updated all 49 JMS578-QGBA0A terminals directly on the schematic component. I only changed Section, Pin Orientation, and Terminal Order; no pin names, pin numbers, replacements, renumbering, or remapping were changed.
Open items:
  • Flux accepted custom section labels like USB3, USB2, SATA, No Connect, and Ground, though some are outside the default autocomplete list.
Suggested next steps:
  1. Add datasheet-derived Pin Type values.
  2. Add Pin Description text for each terminal.
  3. Fix the package metadata/footprint issues flagged earlier.
Fix metadata and pins
Fix metadata
Add pin details
Rebuild footprint
Run review
Sign up to send

Files

Pins

Symbol

Layout

Preview

UAI/GPIO[9]
Pin Number
48
NC_3
Pin Number
25
SSTXN
Pin Number
19
AVDDL_3
Pin Number
24
TXN
Pin Number
33
VCCO_2
Pin Number
39
GND_2
Pin Number
49
RXN
Pin Number
31
VCCK_2
Pin Number
10
XIN
Pin Number
27
GPIO[7]
Pin Number
41
RXP
Pin Number
30
GPIO[5]
Pin Number
9
NC_2
Pin Number
17
VREG_IN
Pin Number
45
AVDDL_5
Pin Number
32
NC_6
Pin Number
47
AVDDL_4
Pin Number
29
GND_1
Pin Number
43
REXT
Pin Number
36
SSRXP
Pin Number
23
GPIO[4]
Pin Number
8
DP
Pin Number
15
NC_1
Pin Number
16
VCCK_3
Pin Number
40
MODE[0]
Pin Number
46
GPIO[0]
Pin Number
2
VCCO_1
Pin Number
7
RST#
Pin Number
38
LXO
Pin Number
44
GPIO[6]
Pin Number
11
UAO/GPIO[8]
Pin Number
37
GPIO[3]
Pin Number
6
AV33O
Pin Number
14
TXP
Pin Number
34
NC_4
Pin Number
26
GPIO[1]
Pin Number
3
XOUT
Pin Number
28
TME
Pin Number
1
MODE[1]
Pin Number
42
VCCK_1
Pin Number
4
SSTXP
Pin Number
20
AVDDL_2
Pin Number
21
DM
Pin Number
13
GPIO[2]
Pin Number
5
AVDDL_1
Pin Number
18
SSRXN
Pin Number
22
VBUS
Pin Number
12
NC_5
Pin Number
35
JMS578QGBA0A Part Review
Date: 2026-07-21
Scope
Reviewed available part metadata, schematic terminals/symbol representation, PCB footprint data, and the configured datasheet for the published Flux part JMS578QGBA0A.
Available Part Metadata

Table

FieldCurrent project valueDatasheet / web checkResult
Manufacturer Part NumberJMS578–QGBA0AJMS578-QGBA0AMismatch risk: project value appears to use an en dash rather than ASCII hyphen. Normalize for sourcing/search.
Manufacturer NameJMicronJMicron Technology CorporationAcceptable, though formal manufacturer is more complete.
DescriptionSuperSpeed USB 3.0 to SATA 6.0Gb/s Bridge ControllerJMS578 is a USB 3.0 / USB 3.1 Gen1 to SATA 6.0Gb/s bridge controllerMatches functionally.
Datasheet URLFlux-hosted uploaded PDFExisting URL is set and was queryable. Official JMicron public PDFs found appear to be product briefs rather than the full QGBA0A pinout/mechanical datasheet.No update performed because a Datasheet URL was already set.
Package or Case CodeTOQFN48, 6 mm × 6 mm, exposed padMismatch: must be QFN48/6x6, not TO.
Pad / pin count49 project terminals/pads48 package pins + exposed ground padCount is acceptable if pad 49 is intended as the exposed GND pad.
Official public JMicron references found during web search:
  • https://www.jmicron.com/file/download/1055/JMS578.pdf
  • https://www.jmicron.com/file/download/1013/JMS578_Product%2BBrief.pdf
Note: the currently attached full PDF appears to contain the detailed QFN48 pinout/mechanical information needed for verification, while the official public links found are product briefs.
Key Datasheet Specs Extracted

Table

CategoryDatasheet value
DeviceJMS578 SuperSpeed USB 3.0 to SATA 6.0Gb/s bridge controller
PackageQFN48, 6 mm × 6 mm, exposed pad
USB supportUSB SuperSpeed / High-Speed / Full-Speed, Mass Storage BOT, UASP
SATA supportSATA II Gen2i/Gen2m, SATA III Gen3
GPIO10 GPIOs, including UART/GPIO pins
External clock30 MHz crystal or reference clock
Crystal tolerance±30 ppm crystal, ±150 ppm onboard long-term stability
Crystal ESR / driveESR max 55 Ω, drive level max 50 µW
VCCO recommended3.0–3.6 V, 3.3 V typical
VCCK recommended1.08–1.32 V, 1.2 V typical
AVDDL recommended1.08–1.32 V, 1.2 V typical
VBUS4.0–5.5 V absolute range
Internal LDO4–5.5 V input, 3.10–3.45 V output, 100 mA max
Internal switch regulator2.25–5.50 V input, 1.05–1.32 V output, 700 mA max
Switch-regulator externals10 µF input cap, 10–20 µF output cap, 4.7 µH inductor
Operating temp0–70 °C ambient, 0–90 °C case, 125 °C max junction
Datasheet Pin Map vs Project Symbol
The project includes 49 terminal components. Datasheet defines 48 QFN pins plus exposed pad. The terminal names and pin numbers mostly match the datasheet.

Table

PinDatasheet signalProject terminalCheck
1TMETMEMatch
2GPIO[0]GPIO[0]Match
3GPIO[1]GPIO[1]Match
4VCCKVCCK_1Match, duplicate supply renamed
5GPIO[2]GPIO[2]Match
6GPIO[3]GPIO[3]Match
7VCCOVCCO_1Match, duplicate supply renamed
8GPIO[4]GPIO[4]Match
9GPIO[5]GPIO[5]Match
10VCCKVCCK_2Match, duplicate supply renamed
11GPIO[6]GPIO[6]Match
12VBUSVBUSMatch
13DMDMMatch
14AV33OAV33OMatch
15DPDPMatch
16NCNC_1Match, should be typed NC
17NCNC_2Match, should be typed NC
18AVDDLAVDDL_1Match, duplicate supply renamed
19SSTXNSSTXNMatch
20SSTXPSSTXPMatch
21AVDDLAVDDL_2Match, duplicate supply renamed
22SSRXNSSRXNMatch
23SSRXPSSRXPMatch
24AVDDLAVDDL_3Match, duplicate supply renamed
25NCNC_3Match, should be typed NC
26NCNC_4Match, should be typed NC
27XINXINMatch
28XOUTXOUTMatch
29AVDDLAVDDL_4Match, duplicate supply renamed
30RXPRXPMatch
31RXNRXNMatch
32AVDDLAVDDL_5Match, duplicate supply renamed
33TXNTXNMatch
34TXPTXPMatch
35NCNC_5Match, should be typed NC
36REXTREXTMatch
37UAO/GPIO[8]UAO/GPIO[8]Match
38RST#RST#Match
39VCCOVCCO_2Match, duplicate supply renamed
40VCCKVCCK_3Match, duplicate supply renamed
41GPIO[7]GPIO[7]Match
42MODE[1]MODE[1]Match
43GNDGND_1Match
44LXOLXOMatch
45VREG_INVREG_INMatch
46MODE[0]MODE[0]Match
47NCNC_6Match, should be typed NC
48UAI/GPIO[9]UAI/GPIO[9]Match
E-PADGNDGND_2 / pin 49Acceptable convention if documented as exposed pad and physically modeled as center GND pad. Currently footprint does not model it correctly.
Pin Descriptions and Electrical Types
All project terminals currently have Pin Type: Unspecified, and no datasheet-derived Pin Description properties were found. This is incomplete for a reusable IC part and reduces ERC/design-review usefulness.
Recommended pin typing:

Table

Signal groupPinsRecommended type/category
VCCO, VCCK, AVDDL, VREG_IN, VBUS4, 7, 10, 12, 18, 21, 24, 29, 32, 39, 40, 45Power input, except AV33O below
AV33O14Power output / analog output
GND, exposed pad43, E-PAD/49Ground
LXO44Power output / switch node
RST#, TME, MODE[0], MODE[1]1, 38, 42, 46Digital input / configuration
GPIO[0:7], UAO/GPIO[8], UAI/GPIO[9]2, 3, 5, 6, 8, 9, 11, 37, 41, 48Digital bidirectional / multifunction
DM, DP13, 15USB2 differential bidirectional analog/digital signal
SSTXP/SSTXN20, 19USB3 SuperSpeed TX outputs
SSRXP/SSRXN23, 22USB3 SuperSpeed RX inputs
TXP/TXN34, 33SATA TX outputs
RXP/RXN30, 31SATA RX inputs
XIN27Clock/analog input
XOUT28Clock/analog output; NC if oscillator input is used
REXT36Analog input / external reference resistor
NC pins16, 17, 25, 26, 35, 47Not Connected
Footprint Cross-Check
Datasheet package dimensions:

Table

ParameterDatasheet value
PackageQFN48
Body size6 mm × 6 mm
Lead pitch0.4 mm BSC
Lead width0.15–0.25 mm, 0.20 mm nominal
Lead length0.35–0.45 mm, 0.40 mm nominal
Exposed pad4.1–4.3 mm × 4.1–4.3 mm, 4.2 mm nominal
Total thickness0.8–0.9 mm
Current PCB footprint data:

Table

Footprint elementCurrent layout valueResult
Pad count49 padsCount aligns with 48 pins + exposed pad, but geometry is invalid.
Pad positionsAll pads at (0,0)Major mismatch.
Pad size0.0016 mm × 0.0016 mm circularMajor mismatch; effectively unusable.
Pad shapeCircular for all padsMajor mismatch for QFN peripheral pads and exposed pad.
Package size0 × 0Major mismatch; should be 6 mm × 6 mm body.
Exposed padNot physically represented as 4.2 mm center padMajor mismatch.
PitchNot representedMajor mismatch; should be 0.4 mm.
Mismatches / Issues to Flag
  1. Package property is wrong: project says TO; datasheet says QFN48 6 mm × 6 mm with exposed pad.
  2. Footprint is not usable: all 49 pads are tiny circular pads at the origin and the package size is zero. It does not implement QFN48 geometry, pitch, lead pads, or center exposed ground pad.
  3. Pin types are incomplete: all terminals are Unspecified; power, ground, NC, high-speed differential, clock, reset/config, and GPIO types should be assigned.
  4. Pin descriptions are missing: datasheet-derived descriptions should be added, especially for multifunction GPIO/SPI/UART pins, regulator pins, REXT, and NC behavior.
  5. MPN normalization issue: current MPN appears to use an en dash (JMS578–QGBA0A) rather than the normal hyphen (JMS578-QGBA0A). This can affect distributor matching and search.
  6. Exposed pad naming: modeling the exposed pad as pin 49 is acceptable, but it should be explicitly described as EPAD/GND and the footprint must include a real 4.2 mm nominal center ground pad.
  7. High-speed metadata missing: USB3/SATA differential-pair pins are present, but no controlled-impedance/differential-pair role metadata is visible on the pins.
Verdict
The schematic terminal names and pin numbers are largely consistent with the datasheet pinout, including the 48 package pins and an additional exposed ground pad. However, the current part should not be considered production-ready because its package metadata and footprint are incorrect, and the symbol lacks pin descriptions and meaningful electrical pin types.
Recommended next fixes:
  1. Normalize MPN to JMS578-QGBA0A.
  2. Change package metadata to QFN48 6 mm × 6 mm exposed-pad package.
  3. Rebuild the footprint as a proper 0.4 mm pitch QFN48 with 4.2 mm nominal exposed pad.
  4. Add datasheet-derived Pin Type and Pin Description properties.
  5. Add differential-pair / controlled-impedance metadata for USB3 and SATA pins if this part will be used for layout/routing.

  • Scope

  • Available Part Metadata

  • Key Datasheet Specs Extracted

  • Datasheet Pin Map vs Project Symbol

  • Pin Descriptions and Electrical Types

  • Footprint Cross-Check

  • Mismatches / Issues to Flag

  • Verdict