ES9822QPRO Review

cherepanyadima

cherepanyadima

Distribute all pins approximately evenly between the Left and Right sides of the schematic symbol.
Place power pins at the Top and first in Terminal Order. Place GND pins at the Bottom, Left, or Right and last in Terminal Order.
Keep related pins together, balance the symbol, and do not change pin names, numbers, or mapping.

flux

I’ll rebalance the existing symbol metadata only: keep power at top/order first, keep GND/EPAD last, and split the remaining functional groups roughly evenly left/right without changing names, numbers, or mappings.

flux

Rebalanced the symbol metadata while preserving all pin names, numbers, and mappings. The non-power/non-ground pins are now split approximately evenly: 14 Left and 15 Right, with power pins Top/orders 1–7 and GND/EPAD Bottom/orders 37–41.
Open items:
  • None for this requested metadata change.
Suggested next steps:
  1. Review the rendered symbol for visual spacing.
  2. Optionally correct labels for pin 40 (RT1) and pin 41 (EPAD) in a separate pass.
Fix labels and review
Correct pin labels
Populate pin metadata
Run ERC review
Check symbol layout
GPIO10
Pin Number
1
GPIO11
Pin Number
2
GPIO4
Pin Number
36
AVCC_R
Pin Number
21
IN_P1
Pin Number
12
SS/ADDR1
Pin Number
27
AGND
Pin Number
6
GPIO2
Pin Number
38
DGND_1
Pin Number
31
VREF_R
Pin Number
22
NC_1
Pin Number
14
ACLK
Pin Number
4
GPIO3
Pin Number
37
IN_P2
Pin Number
19
GPIO8
Pin Number
32
SCLK/SCL
Pin Number
26
AVCC_L
Pin Number
10
GPIO6
Pin Number
34
GPIO5
Pin Number
35
XOUT
Pin Number
7
NC_2
Pin Number
15
GPIO1
Pin Number
39
MOSI/SDA
Pin Number
25
IN_M2
Pin Number
18
IN_M1
Pin Number
13
DGND_2
Pin Number
40
AVCC
Pin Number
5
AVDD
Pin Number
30
GPIO7
Pin Number
33
CHIP_EN
Pin Number
23
DGND_3
Pin Number
41
VREF_L
Pin Number
9
AGND_R
Pin Number
20
GPIO9
Pin Number
24
NC_3
Pin Number
16
XIN
Pin Number
8
DVDD
Pin Number
29
MODE
Pin Number
3
AGND_L
Pin Number
11
NC_4
Pin Number
17
MISO/ADDR2
Pin Number
28

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Part Review - ES9822QPRO
Date: 2026-07-15
Scope
Reviewed the published Flux part project for ES9822QPRO against the available part metadata, schematic terminals, footprint pads, and the official ESS Technology datasheet.
Datasheet Source
  • Previous Datasheet URL property: https://www.esstech.com/wp-content/uploads/2022/09/ES9822PRO_DS_v0.3.pdf
    • Web scrape result: ESS page returned “Page not found”.
  • Updated Datasheet URL property: https://www.esstech.com/wp-content/uploads/2025/04/ES9822PRO_DS_v0.5.2.pdf
    • Official ESS Technology domain, ES9822 PRO Product Datasheet, Version 0.5.2, April 2025.
    • Mouser mirror used for text extraction where the ESS-hosted PDF required verification: https://www.mouser.com/datasheet/2/1082/ES9822PRO_DS_v0_5_2-3623520.pdf
Current Part Metadata

Table

FieldCurrent valueDatasheet check
Manufacturer Part NumberES9822QPROMatches ordering information
ManufacturerESS TechnologyMatches datasheet publisher
DescriptionAnalog to Digital Converters - ADC Sabre stereo reference PRO ADC5 mm x 5mm, 40 pin QFNFunction/package broadly match; wording has missing space before “5 mm”
Package or Case Code40-QFNMatches 5 mm x 5 mm 40 QFN ordering information
Designator PrefixICAppropriate
Pads41Matches 40 perimeter pins + Pin 41 exposed/package pad
Key Datasheet Specs

Table

SpecValue
PartES9822QPRO / ES9822 PRO
FunctionSABRE 32-bit, high-performance 2-channel ADC with programmable filters, ASP, and multiple output formats
Package5 mm x 5 mm 40 QFN, exposed/package pad numbered Pin 41
Version reviewedDatasheet v0.5.2, April 2025
Dynamic range+125 dB DNR in 2-channel mode; +128 dB DNR in mono mode
THD+N-117 dB in 2-channel mode; -118 dB in mono mode
Sample rates / formatsPCM up to 768 kHz; DSD up to DSD1024 in v0.5.2 text; TDM/I2S/DSD/S/PDIF/RAW formats
Typical powerLess than 170 mW stated in overview
SuppliesAVCC/AVCC_L/AVCC_R = 4.5 V; AVDD = 3.3 V; DVDD internally supplied
Operating temperature-20 °C to +85 °C
Minimum MCLK22 MHz
Exposed padPin 41, not electrically connected internally, used for heat dissipation; connect to DGND/GND
Pinout Cross-Check
The schematic uses one Terminal component per package pin. Pins 1-39 match the v0.5.2 datasheet by pin number and functional name, allowing suffixes such as NC_1...NC_4 and DGND_1 for duplicate names.

Table

PinSchematic terminalDatasheet nameResultNotes
1GPIO10GPIO10OKGeneral I/O
2GPIO11GPIO11OKGeneral I/O
3MODEMODEOKI2C/SPI control selection
4ACLKACLKOKAuxiliary clock input
5AVCCAVCCOK4.5 V supply
6AGNDAGNDOKAnalog ground
7XOUTXOUTOKCrystal output
8XINXINOKCrystal/oscillator input; datasheet footnote says MCLK can connect to XIN or ACLK
9VREF_LVREF_LOKLow-noise reference
10AVCC_LAVCC_LOKADC reference 4.5 V supply
11AGND_LAGND_LOKAnalog ground
12IN_P1IN_P1OKCh1 positive input
13IN_M1IN_M1OKCh1 negative input
14NC_1NCOK with naming suffixNo connect
15NC_2NCOK with naming suffixNo connect
16NC_3NCOK with naming suffixNo connect
17NC_4NCOK with naming suffixNo connect
18IN_M2IN_M2OKCh2 negative input
19IN_P2IN_P2OKCh2 positive input
20AGND_RAGND_ROKAnalog ground
21AVCC_RAVCC_ROKADC reference 4.5 V supply
22VREF_RVREF_ROKLow-noise reference
23CHIP_ENCHIP_ENOKActive-high chip enable
24GPIO9GPIO9OKGPIO / interrupt capable
25MOSI/SDAMOSI/SDAOKSPI MOSI or I2C SDA
26SCLK/SCLSCLK/SCLOKSPI/I2C serial clock
27SS/ADDR1SS/ADDR1OKSPI SS or I2C ADDR1
28MISO/ADDR2MISO/ADDR2OKSPI MISO or I2C ADDR2; v0.5.2 specifically corrected this pin
29DVDDDVDDOKDigital core supply, internally supplied
30AVDDAVDDOK3.3 V I/O supply
31DGND_1DGNDOK with naming suffixDigital core ground
32GPIO8GPIO8OKSerial data 8
33GPIO7GPIO7OKSerial data 7
34GPIO6GPIO6OKSerial data 6
35GPIO5GPIO5OKSerial data 5
36GPIO4GPIO4OKSerial data 4
37GPIO3GPIO3OKSerial data 3
38GPIO2GPIO2OKSerial data 2
39GPIO1GPIO1OKSerial data 1
40DGND_2RT1MISMATCHDatasheet v0.5.2: RT1, input, HiZ, reserved; must be connected to DGND for normal operation. The schematic currently labels this pin as DGND_2, which hides the required reserved-pin function.
41DGND_3Package Pad / EPADMISMATCHDatasheet: exposed/package pad, not electrically connected internally; connect to DGND/GND. Current label DGND_3 makes it look like a normal digital ground pin.
Symbol and Pin Property Findings
  • Pin numbering is present on every terminal and the symbol has 41 terminals, matching the datasheet pad count.
  • All terminal Pin Type properties are currently Unspecified; the datasheet defines analog inputs, analog output, I/O pins, power pins, ground pins, no-connect pins, reserved input, and package pad.
  • No terminal Pin Description properties are populated. Adding datasheet descriptions would improve ERC, searchability, and part quality.
  • Duplicate-style labels such as NC_1...NC_4 and DGND_1 are acceptable Flux disambiguation, but pin 40 and pin 41 should not use ground-like names.
Footprint Cross-Check

Table

Footprint itemCurrent footprintDatasheet checkResult
Body/silkscreen outline5 mm x 5 mm outline visibleD/E = 5.00 mm BSCOK
Perimeter pad count40 perimeter pads40 QFN perimeter pinsOK
Exposed pad1 center padPin 41 package pad / EPADOK count/location
PitchPads spaced on 0.40 mm gride = 0.40 mm BSCOK
Perimeter pad width0.20 mm nominal from footprint datab = 0.15/0.20/0.25 mmOK nominal
Exposed pad size3.84 mm x 3.84 mm from footprint dataD2/E2 = 3.74 min / 3.79 nom / 3.84 max mmOK at datasheet max
Pin-1 markerMarker at pin-1 corner presentPin-1 indicator required for QFN orientationOK
Note: the layout tree displayed very small numeric pad dimensions due to a unit-scaling presentation issue, but the footprint geometry and silkscreen indicate the intended 5 mm QFN footprint with 0.40 mm pitch and 3.84 mm EPAD.
Mismatches / Recommended Fixes
  1. Pin 40 label is incorrect for current datasheet v0.5.2. Rename schematic terminal/pad from DGND_2 to RT1, set pin type to Input, and add pin description: “Reserved. Must be connected to DGND for normal operation.”
  2. Pin 41 exposed pad label is misleading. Rename from DGND_3 to EPAD or Package Pad, set pin type to Passive or Unspecified, and add description: “Not electrically connected internally, used for heat dissipation. Connect to DGND/GND.”
  3. Pin types are missing across the symbol. Populate Pin Type according to datasheet: Power, Ground, Input, Output/Analog Output, I/O, Not Connected, Passive/Unspecified for EPAD.
  4. Pin descriptions are missing across the symbol. Populate descriptions from Table 1.
  5. Description wording could be cleaned up. Suggested: “SABRE 32-bit high-performance 2-channel ADC, 5 mm x 5 mm 40-QFN.”
Overall Assessment
The part metadata, package family, pad count, and footprint geometry are broadly correct for ES9822QPRO. The main datasheet-derived mismatches are in the schematic symbol metadata: pin 40 is RT1 rather than DGND, pin 41 is the exposed package pad rather than a normal DGND pin, and all terminal pin types/descriptions are missing.

  • Scope

  • Datasheet Source

  • Current Part Metadata

  • Key Datasheet Specs

  • Pinout Cross-Check

  • Symbol and Pin Property Findings

  • Footprint Cross-Check

  • Mismatches / Recommended Fixes

  • Overall Assessment

Documents

Assets

kicad_mod

ES9822QPRO

QFN40P500X500X80-41N-D.kicad_modFootprint
ES9822QPRO

ES9822QPRO

ES9822QPRO.stp3D Model
image3.png

image3.png

image3Thumbnail
kicad_mod

F_QFN40P500X500X80-41N-D.kicad_mod

F_QFN40P500X500X80-41N-D
kicad_mod

F1_QFN40P500X500X80-41N-D.kicad_mod

F1_QFN40P500X500X80-41N-D
svg

ES9822QPRO

ES9822QPRO Symbol.svgDefault

ES9822QPRO

ES9822QPRO thumbnail
Analog to Digital Converters - ADC Sabre stereo reference PRO ADC5 mm x 5mm, 40 pin QFN

Properties

ES9822QPRO

ESS Technology

Integrated Circuit

esstech.com/wp-content/uploads/2025/04/ES9822PRO_DS_v0.5.2.pdf

IC

40-QFN

parametric-v1

Pricing & Availability

DPN

Stock

Qty 1

1

794

$10.20

Controls