Part Audit Review

flux

I’ll correct the package designation, populate datasheet-based electrical types and descriptions for all 49 terminals, then re-inspect the part to verify the updates.
Thought for 3 mins 48 sec
Thought for 9 sec
Referenced guidance.
1/3 Correct package metadata to 48-QFN / PG-VQFN-48

Correct package metadata to 48-QFN / PG-VQFN-48

Populate electrical types and datasheet pin descriptions for all 49 terminals

Verify package metadata and every terminal property

Thought for 13 sec
Thought for 7 sec
Awaiting 1 background task
Thought for 7 sec
Checking CYPM1311 Pin Metadata progress…
Received notification from "CYPM1311 Pin Metadata" that it finished — picking the work back up.

flux

The executor reports completion. I’m reconciling it now by independently checking the package value and all 49 terminal types/descriptions before closing.

flux

Corrected and verified:
  • Package metadata: 48-QFN (PG-VQFN-48, 6 × 6 mm, 0.40 mm pitch)
  • All 49 terminals now have datasheet-based electrical types
  • All terminals now have detailed pin descriptions and alternate functions
  • Pin numbering, names, orientations, symbol positions, and footprint mappings were preserved
  • No terminals remain typed as Unspecified
Fix remaining metadata
Review exposed-pad footprint
Update part audit
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Files

Pins

Symbol

Layout

Preview

P2.4
Pin Number
45
XRES
Pin Number
33
CC1
Pin Number
28
VBUS_OUT_CTRL
Pin Number
26
VBUS_C
Pin Number
31
P1.5
Pin Number
21
P3.5
Pin Number
3
P4.1
Pin Number
35
P5.1
Pin Number
8
USBDP
Pin Number
39
VSS_2
Pin Number
32
VSYS
Pin Number
36
CSP
Pin Number
38
P6.0
Pin Number
15
VDDD
Pin Number
43
VDDIO_2
Pin Number
42
CSN
Pin Number
37
P6.3
Pin Number
19
P5.2
Pin Number
9
P3.0
Pin Number
1
VBUS_IN_CTRL
Pin Number
27
VCONN_SOURCE
Pin Number
29
EP
Pin Number
49
P2.3
Pin Number
46
VSS_1
Pin Number
6
USBDM
Pin Number
40
P6.2
Pin Number
18
P1.2
Pin Number
13
P4.0
Pin Number
34
P1.1
Pin Number
12
VCCD
Pin Number
41
VBUS_IN_NGDO
Pin Number
24
P3.6
Pin Number
4
P2.2
Pin Number
47
P5.3
Pin Number
10
P5.5
Pin Number
11
P1.6
Pin Number
22
P0.0
Pin Number
17
VDDA
Pin Number
5
P3.3
Pin Number
2
VDDIO_1
Pin Number
23
P2.1
Pin Number
48
CC2
Pin Number
30
VBUS_OUT_NGDO
Pin Number
25
P1.3
Pin Number
14
VSS_3
Pin Number
44
P6.1
Pin Number
16
P1.4
Pin Number
20
P5.0
Pin Number
7
Part Audit Report
Scope
Audit of project metadata, schematic symbol, terminal numbering/names, PCB footprint, and available official manufacturer documentation for CYPM1311-48LDXI.
Source reviewed
Current part information

Table

FieldCurrent valueAudit result
MPNCYPM1311-48LDXIMatches ordering information
ManufacturerInfineonCorrect
Part typeIntegrated CircuitsBroad but acceptable; Microcontroller would be more specific
DescriptionArm Cortex-M0+ EZ-PD PMG1 MCU, 48 MHz, 256 KB flash, 48-QFN (6 × 6 mm)Substantially correct, but omits major USB-C/PD and analog features
Datasheet URLOfficial Infineon PDF is already setNo URL update was required
Package property32-QFNIncorrect
Logical terminals49Correct when counting 48 perimeter leads plus exposed pad
FootprintQFN40P600X600X60-49N-DConsistent with 0.40 mm pitch, 6 × 6 mm body, 48 leads plus EP
Key specifications
  • 48 MHz Arm Cortex-M0+ CPU with DMA.
  • 256 KB flash, 32 KB SRAM, and 96 KB ROM containing PD code.
  • Single USB Type-C / USB-PD dual-role port for this ordering variant; USB-PD 3.2 and EPR support up to 28 V.
  • Full-speed USB 2.0 device PHY.
  • 26 GPIOs on the 48-QFN variant, including fail-safe I/O capability.
  • Seven SCBs on the 48-QFN variant, configurable for I2C/SPI/UART with variant-specific limitations.
  • One 12-bit SAR ADC, two 8-bit SAR ADCs, two op-amps, and two low-power comparators.
  • VSYS operating supply: 2.8–5.5 V for UFP use and 3.0–5.5 V for DFP/DRP use.
  • VDDIO: 1.71 V up to VDDD; VDDA must be tied to VDDD at board level.
  • High-voltage VBUS monitoring/control pins support approximately 4–30 V ranges depending on the pin/function.
  • Industrial ambient temperature range: -40 °C to +85 °C.
  • Package: 48-lead QFN / PG-VQFN-48, 6.0 × 6.0 × 0.6 mm, 0.40 mm lead pitch, exposed pad nominally 4.6 × 4.6 mm.
Symbol and pin audit
Result
All 49 symbol terminals are present, and the terminal numbers and primary pin names match the datasheet pin table, including pin 49 as the exposed pad.
Deficiencies
  • Every terminal currently has Pin Type = Unspecified. Power, ground, reset, USB, CC, current-sense, control-output, and GPIO pins should have meaningful electrical types for ERC.
  • Every terminal lacks a Pin Description. The datasheet provides detailed functions and alternate-function information, but none is stored in the part.
  • Several symbol names are shortened from the datasheet, for example VSS_1/2/3, VDDIO_1/2, CC1, CC2, CSN, and CSP. These are not numbering errors, but descriptions should identify the port and function.
  • The exposed pad EP should be described and typed as ground/thermal ground according to the manufacturer's package requirements.
Footprint audit
Matches
  • 48 perimeter pads plus one exposed pad are present.
  • Lead pitch is 0.40 mm.
  • Body outline is 6 × 6 mm.
  • Perimeter copper pad width is 0.20 mm, consistent with the nominal lead width.
  • The central EP is 4.7 × 4.7 mm, within the package exposed-pad maximum dimension.
Risks / mismatches
  • The project-level Package or Case Code = 32-QFN conflicts with both the MPN and footprint and must be changed to 48-QFN / PG-VQFN-48.
  • The footprint description says 0.6m; this is a text typo and should read 0.6 mm.
  • The exposed copper pad is 4.7 × 4.7 mm, equal to the maximum package EP size. This may leave no dimensional margin at the worst case. A nominal 4.6 × 4.6 mm land, or a manufacturer-qualified land-pattern value, is safer unless assembly guidance specifies otherwise.
  • The exposed pad uses one solid paste opening equal to the full copper area. For a large QFN EP, a segmented/windowed paste stencil is normally preferred to control solder volume and voiding. The datasheet package drawing does not provide a recommended land/stencil pattern, so this should be validated against Infineon package application guidance and the assembler's process.
  • Courtyard is 7.25 × 7.25 mm, which is conservative and not an electrical mismatch.
Mismatch summary
  1. Definite: Package property incorrectly says 32-QFN; actual package is 48-QFN / PG-VQFN-48.
  2. Definite: All terminal electrical types are unspecified.
  3. Definite: All terminal descriptions are missing.
  4. Minor: Footprint description contains a unit typo (0.6m).
  5. Manufacturing risk: EP land is at the package maximum and paste is not windowed; verify or revise using qualified package/assembly guidance.
  6. No mismatch found: MPN, manufacturer, datasheet URL, terminal count, primary pin names, pin numbers, package body size, and 0.40 mm pitch.
  • Change Package or Case Code from 32-QFN to 48-QFN (PG-VQFN-48, 6 × 6 mm, 0.40 mm pitch).
  • Populate every terminal's Pin Description and assign ERC-relevant Pin Type values.
  • Correct the footprint description unit typo.
  • Review the EP copper and stencil geometry with Infineon's package application note or the intended PCB assembler before production release.

  • Scope

  • Source reviewed

  • Current part information

  • Key specifications

  • Symbol and pin audit

  • Result

  • Deficiencies

  • Footprint audit

  • Matches

  • Risks / mismatches

  • Mismatch summary

  • Recommended corrections