CMX7341Q3 Review
Assign Terminal Order and Pin Orientation, then run a schematic/symbol review.
Thought for 7 sec
I’ll assign terminal ordering/orientation by functional group, then inspect the symbol metadata for consistency and remaining issues.
Worked for 4 mins 41 sec
Assigned Pin Orientation and Terminal Order across all 49 terminals, then verified the symbol metadata.
Open items:
- Power pins are Top / order 1; ground and substrate are Bottom / order 10.
- Remaining groups are distributed Left/Right consistently by function.
- The available schematic/symbol review checks returned no reported issues for the requested symbol/terminal checks.
Suggested next steps:
- Visually inspect the generated symbol layout.
- Publish/update the part if the layout looks correct.
- Optionally review the footprint paste/thermal pad next.
Inspect and publish
Inspect symbol layout
Review thermal pad
Publish the part
Run full checks
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Part Datasheet Review — CMX7341Q3
Date: 2026-07-20
Scope
Reviewed available part-project information for CML Micro CMX7341Q3: project metadata/properties, schematic terminal symbol, PCB footprint, and datasheet-derived pin/package/specification data.
Sources
- Current project Datasheet URL property:
https://storage.googleapis.com/graviton-electric-symbols/document_assets/user-uploaded/f0bc5e4b0c377eb3455c051ffef27aa60216d6d3b4bb9290a73043d1e7ac4b3a.pdf - The existing PDF identifies as: CMX7241/CMX7341 PMR Common Platform Processor, document code D/7241_7341_FI1.x/5, November 2015.
- Official CML Micro FI-1.x datasheet located during review:
https://cmlmicro.com/Content/Downloads/CMX7241_7341_FI-1_ds.pdf
The Datasheet URL property was already populated, so no Datasheet URL update was required by the user's conditional instruction. Note: the populated URL is an uploaded copy rather than a direct
cmlmicro.com URL.Available part information found in project
Table
| Field | Project value | Datasheet / review result |
|---|---|---|
| Manufacturer Part Number | CMX7341Q3 | Matches datasheet ordering information. |
| Manufacturer Name | CML Micro | Matches CML Micro / CML Microsystems datasheet source. |
| Description | RF Wireless Misc PMR/LMR Platform Processor | Consistent, though datasheet wording is more specific: PMR Common Platform Processor, dPMR and analogue PMR processor with Rx I/Q support. |
| Part Type | Processor | Acceptable but broad; a more specific taxonomy would be communications/RF modem/baseband/platform processor if available. |
| Designator Prefix | IC | Appropriate for an integrated circuit. |
| Datasheet URL | Uploaded PDF URL | Present; official CML equivalent found. |
| Mount | Wire | Mismatch: package is surface-mount VQFN/QFN, not wire-mounted. |
| Pin / pad count | 49 terminals/pads | Matches 48-lead VQFN plus exposed metal pad/substrate. |
| Package / footprint | Footprint asset QFN50P700X700X100-49N-D.kicad_mod | Consistent with 7 mm x 7 mm, 0.5 mm pitch, 48-lead VQFN with exposed pad. |
Key datasheet specifications
Table
| Specification | Datasheet value |
|---|---|
| Device family/function | CMX7241/CMX7341 PMR Common Platform Processor; FI-1.x supports dPMR and analogue PMR processing. |
| CMX7341 distinction | Differential input version; CMX7341 is VQFN only. |
| Package | Q3: 48-lead VQFN with exposed metal pad. |
| Ordering part number | CMX7341Q3. |
| Supply voltage operating range | DVDD-DVSS: 3.0 V to 3.6 V; AVDD-AVSS: 3.0 V to 3.6 V. |
| Absolute max supply | DVDD-DVSS: -0.3 V to 4.0 V; AVDD-AVSS: -0.3 V to 4.0 V. |
| Voltage differential limits | DVDD vs AVDD: 0 to 0.3 V; DVSS vs AVSS: 0 to 50 mV. |
| Operating temperature | -40 °C to +85 °C. |
| Package power dissipation | Q3: 1750 mW at 25 °C, derate 17.5 mW/°C. |
| Clock | FI-1.x assumes/requires 19.2 MHz external clock for default function image operation; XTAL/CLK supports external clock or crystal mode per datasheet limits. |
| VDEC | Internal 1.8 V digital supply output/decoupling node; no other loads. |
| VBIAS | Approx. AVDD/2 internal bias; decouple to AVSS, no other load unless buffered. |
| Host interface | C-BUS serial interface compatible with Microwire/SPI using CSN, SCLK, CDATA, RDATA, IRQN. |
Symbol and pin cross-check
Result
The schematic terminal names and pin numbers match the CMX7341Q3 datasheet pin table for all 48 perimeter leads plus the exposed pad.
Table
| Pin | Symbol terminal | Datasheet name | Datasheet type | Datasheet description summary | Result |
|---|---|---|---|---|---|
| 1 | EPSI | EPSI | OP | Auxiliary SPI/C-BUS serial data output | Match |
| 2 | EPSCLK | EPSCLK | OP | Auxiliary SPI/C-BUS serial clock output | Match |
| 3 | EPSO | EPSO | IP+PD | Auxiliary SPI/C-BUS serial data input | Match |
| 4 | EPCSN | EPCSN | OP | Serial chip select for CMX994 | Match |
| 5 | BOOTEN1 | BOOTEN1 | IP+PD | Bootstrap mode select with BOOTEN2 | Match |
| 6 | BOOTEN2 | BOOTEN2 | IP+PD | Bootstrap mode select with BOOTEN1 | Match |
| 7 | RESET | RESET | PWR | Dedicated active-high reset; tie to DVSS if unused | Match |
| 8 | IRQN | IRQN | OP | Wire-ORable interrupt output; external pull-up required | Match |
| 9 | VDEC_1 | VDEC | PWR | Internal 1.8 V digital supply; decouple only | Match; duplicate name suffix acceptable |
| 10 | RXENA | RXENA | OP | Rx enable output | Match |
| 11 | GPIOA | GPIOA | BI | General-purpose I/O | Match |
| 12 | GPIOB | GPIOB | BI | General-purpose I/O | Match |
| 13 | SYSCLK1 | SYSCLK1 | OP | Synthesised system clock output 1 | Match |
| 14 | DVSS_1 | DVSS | PWR | Digital ground | Match; duplicate name suffix acceptable |
| 15 | TXENA | TXENA | OP | Tx enable output | Match |
| 16 | DISCPOS | DISCPOS | IP | Differential input 1 positive / I input | Match |
| 17 | DISCNEG | DISCNEG | IP | Differential input 1 negative / I input | Match |
| 18 | DISCFB | DISCFB | OP | Input 1 amplifier feedback | Match |
| 19 | ALTPOS | ALTPOS | IP | Differential input 2 positive / Q input | Match |
| 20 | ALTNEG | ALTNEG | IP | Differential input 2 negative / Q input | Match |
| 21 | ALTFB | ALTFB | OP | Input 2 amplifier feedback | Match |
| 22 | MICFB | MICFB | OP | Microphone input amplifier feedback | Match |
| 23 | MIC | MIC | IP | Microphone inverting input | Match |
| 24 | MOD1 | MOD1 | OP | Modulator 1 output | Match |
| 25 | MOD2 | MOD2 | OP | Modulator 2 output | Match |
| 26 | VBIAS | VBIAS | OP | Internal bias approx. AVDD/2; decouple to AVSS | Match |
| 27 | AUDIO | AUDIO | OP | Audio output in SPI-Codec mode | Match |
| 28 | ADC1 | ADC1 | IP | Auxiliary ADC input 1 | Match |
| 29 | ADC2 | ADC2 | IP | Auxiliary ADC input 2 | Match |
| 30 | ADC3 | ADC3 | IP | Auxiliary ADC input 3 | Match |
| 31 | ADC4 | ADC4 | IP | Auxiliary ADC input 4 | Match |
| 32 | AVDD | AVDD | PWR | Analogue +3.3 V supply | Match |
| 33 | DAC1 | DAC1 | OP | Auxiliary DAC output 1 / RAMDAC | Match |
| 34 | DAC2 | DAC2 | OP | Auxiliary DAC output 2 / tone generator | Match |
| 35 | DAC3 | DAC3 | OP | Auxiliary DAC output 3 for FI-1 | Match |
| 36 | DAC4 | DAC4 | OP | Auxiliary DAC output 4 | Match |
| 37 | DVSS_2 | DVSS | PWR | Digital ground | Match; duplicate name suffix acceptable |
| 38 | VDEC_2 | VDEC | PWR | Internal 1.8 V supply; decouple only | Match; duplicate name suffix acceptable |
| 39 | XTAL/CLK | XTAL/CLK | IP | External clock or crystal input | Match |
| 40 | XTALN | XTALN | OP | Crystal oscillator inverter output; NC if external clock used | Match |
| 41 | DVDD | DVDD | PWR | Digital +3.3 V supply | Match |
| 42 | CDATA | CDATA | IP | Host C-BUS command data input from microcontroller | Match |
| 43 | RDATA | RDATA | TS OP | Host C-BUS tri-state reply data output | Match |
| 44 | SSOUT | SSOUT | OP | Serial chip select for CMX6x8/CMX7262 or frame sync | Match |
| 45 | DVSS_3 | DVSS | PWR | Digital ground | Match; duplicate name suffix acceptable |
| 46 | SCLK | SCLK | IP | Host C-BUS serial clock input | Match |
| 47 | SYSCLK2 | SYSCLK2 | OP | Synthesised system clock output 2 | Match |
| 48 | CSN | CSN | IP | Host C-BUS chip select input; no internal pull-up | Match |
| 49 | SUBSTRATE | SUBSTRATE / exposed pad | ~ | Exposed metal pad; must connect to analogue ground AVSS | Match, with critical connection note |
Symbol metadata issues
- Pin Type is
Unspecifiedfor every terminal. This does not match datasheet electrical types and reduces ERC usefulness. - Pin Description properties are missing. The datasheet provides meaningful descriptions for every pin; these should be added for part quality.
- Pin Group / Section metadata is absent. The symbol can be improved by grouping pins into broad functions such as Power, Ground, Host C-BUS, Auxiliary SPI/C-BUS, Boot/Reset/IRQ, Clock, Analog Inputs, Audio/Modulator Outputs, Auxiliary ADC/DAC, and Substrate.
- Pin 49 SUBSTRATE needs an explicit description: exposed pad must connect to analogue ground/AVSS. This is a critical application constraint.
Footprint cross-check
Footprint information found
- Footprint asset:
QFN50P700X700X100-49N-D.kicad_mod - Description:
48-lead VQFN (Q3) - Body/fab outline: 7.0 mm x 7.0 mm
- Pitch: 0.50 mm
- Perimeter pads: 48 pads, 0.30 mm x 0.85 mm, centers at ±3.45 mm around package
- Exposed pad: pad 49, 5.65 mm x 5.65 mm
- 3D model:
CMX7341Q3.stp
Datasheet package information
- Package: Q3, 48-lead VQFN
- Body size: 7.00 mm BSC x 7.00 mm BSC
- Pitch: 0.50 mm
- Lead length L: 0.30 mm to 0.50 mm
- Exposed metal pad dimensions F/G: 4.60 mm to 5.65 mm
- Datasheet states package dimensions may change and recommends checking CML packaging information.
Footprint result
The footprint is broadly consistent with the datasheet package: 48 perimeter pads + exposed pad, 7 mm body, 0.5 mm pitch, and central exposed pad.
Footprint caveats:
- The datasheet excerpt provides mechanical package dimensions, not a complete recommended PCB land pattern. Pad size and paste should be verified against any latest CML package/land-pattern guidance.
- The exposed pad copper is 5.65 mm x 5.65 mm, equal to the maximum exposed metal pad dimension reported by the datasheet. This is plausible but should be checked against a recommended land pattern.
- The exposed pad has one large paste aperture in the imported KiCad footprint. For manufacturability, paste windowing/segmentation is usually preferred on large QFN thermal pads to reduce voiding and package float.
- The footprint name
QFN50P700X700X100-49N-Dis not a mismatch:50Pindicates 0.50 mm pitch, and49Ncorresponds to 48 leads plus exposed pad.
Mismatches / issues to flag
Table
| Severity | Issue | Detail | Recommended action |
|---|---|---|---|
| High | Mount property is wrong | Project property says Mount: Wire, but the package is surface-mount 48-lead VQFN/QFN. | Change Mount to SMD / Surface Mount if editable. |
| High | Pin types unspecified | Every terminal has Pin Type: Unspecified; datasheet defines IP, OP, BI, TS OP, and PWR pins. | Populate Pin Type from datasheet-derived functions. |
| High | Pin descriptions missing | No terminal has a Pin Description; datasheet descriptions are available. | Add descriptions for all pins, especially supplies, VDEC, VBIAS, RESET, IRQN, BOOTEN, C-BUS, XTAL, and SUBSTRATE. |
| High | SUBSTRATE connection requirement not encoded | Pin 49 must connect to analogue ground AVSS; current symbol name alone does not communicate this. | Add Pin Description and consider Ground/Power pin typing for SUBSTRATE. |
| Medium | Datasheet URL is uploaded copy, not direct official URL | Existing Datasheet URL is populated but points to Google Cloud Storage; official CML URL was found. | Optionally replace with official CML FI-1.x datasheet URL. |
| Medium | Package property not explicit | Package is represented by footprint asset, but no visible project property such as Package or Case Code was found in metadata. | Add/confirm package metadata as 48-lead VQFN/Q3, 7 mm x 7 mm, 0.5 mm pitch. |
| Medium | Exposed pad paste aperture likely needs refinement | Imported footprint appears to use one large exposed-pad paste aperture. | Verify against assembly house rules or segment paste. |
| Low | Part Type is broad | Processor is not wrong, but the device is a specialized PMR/dPMR platform processor/baseband IC. | Use a more specific category if available. |
Overall conclusion
The pin numbering, pin names, pin count, and general Q3 VQFN footprint geometry are consistent with the datasheet for CMX7341Q3. The main quality issues are metadata-related rather than pinout-related: Mount is incorrect, pin types and pin descriptions are missing, SUBSTRATE's AVSS connection requirement should be explicit, and the exposed-pad land/paste implementation should be checked against the latest CML package guidance.
Scope
Sources
Available part information found in project
Key datasheet specifications
Symbol and pin cross-check
Result
Symbol metadata issues
Footprint cross-check
Footprint information found
Datasheet package information
Footprint result
Mismatches / issues to flag
Overall conclusion
