Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.
I’ll audit the part metadata, locate the official Nexperia datasheet if needed, verify the symbol and footprint against it, then update the Datasheet property and document any mismatches.
The project currently has six terminals but no PCB pads or footprint geometry. I’m now validating the exact Nexperia package pinout and specifications from the official datasheet.
The Datasheet URL is already set to the official Nexperia PDF, so no property change is needed. I found major symbol/footprint-state issues and am updating the audit report with the verified details.
Audit complete. The official Nexperia datasheet URL was already set, so no property update was needed. Major issues: six independent symbol terminals instead of three electrical nodes, missing pin descriptions, and no pads/active footprint geometry; I filed an internal part-quality report.
Flux Part UID:bcede1d3-bb00-4160-a848-aca1645fb72a
The official Nexperia datasheet explicitly covers ordering code BUK6Y14-40PX. The project Datasheet URL was already set to the official PDF, so no update was required.
Current project-level properties
Present: Manufacturer Name, Manufacturer Part Number, Datasheet URL, Symbol Style (parametric-v1), Part Type (MOSFET), Mount (Surface Mount), and Designator Prefix (Q).
Not present as explicit project properties: Package/Case, Machine Datasheet URL, pin count, and the detailed electrical ratings. Package information is nevertheless identifiable from the device datasheet and project assets.
Datasheet pinout
Table
Physical terminal
Function
1
Source
2
Source
3
Source
4
Gate
Mounting base (mb)
Drain
The package has four numbered leads plus one unnumbered drain mounting base, and only three electrical nodes: Source, Gate, and Drain.
Schematic symbol audit
The current symbol exposes six independent passive terminals:
Table
Symbol terminal
Pin number
Current description
S_1
1
Missing
S_2
2
Missing
S_3
3
Missing
G
4
Missing
D_1
5
Missing
D_2
6
Missing
Symbol mismatches
Pins 1–3 and pin 4 correspond to the datasheet source and gate leads.
Pins 5 and 6 are not official package pin numbers; the datasheet defines a single unnumbered drain mounting base.
The three Source terminals are modeled as separate electrical terminals rather than one internally common Source node.
The two Drain terminals are modeled separately rather than one internally common Drain node.
Pin descriptions are missing.
The symbol does not communicate P-channel polarity, body-diode orientation, or the internally common terminals.
Risk: a design can accidentally route only part of the Source or Drain copper, or assign split drain pads to different nets.
Footprint audit
The current live PCB layout contains zero pads and no instantiated footprint geometry. Therefore the footprint cannot presently be validated or used for PCB placement from the active part state.
The project contains KiCad footprint and STEP assets, and an earlier audit identified a six-pad representation with 1.27 mm lead pitch and split Drain geometry. However, because those pads are not present in the current live layout, their copper, solder-mask, paste, courtyard, and 3D seating cannot be certified from the active part.
Datasheet package reference
SOT669 / LFPAK56 key package limits include:
Overall length D: 5.8–6.2 mm
Package height A: 1.20 mm max
Lead pitch e: 1.27 mm
Lead width b: 0.35–0.50 mm
Lead length L: 0.7–0.9 mm
Source/gate side and drain mounting-base geometry must follow the Nexperia SOT669 package and reflow-footprint drawings.
Key electrical and thermal specifications
Table
Parameter
Datasheet value and conditions
VDS
−40 V max
VGS
−20 to +20 V
Continuous ID
−64 A, VGS = −10 V, Tmb = 25 °C
Continuous ID
−46 A, VGS = −10 V, Tmb = 100 °C
Pulsed IDM
−257 A, single pulse, tp ≤ 10 µs, Tmb = 25 °C
Total power dissipation
110 W, Tmb = 25 °C
Junction temperature
−55 to +175 °C
RDS(on)
11 mΩ typ, 14 mΩ max, VGS = −10 V, ID = −10.8 A, Tj = 25 °C
RDS(on), 4.5 V drive
17 mΩ typ, 25 mΩ max, VGS = −4.5 V, ID = −8.1 A, Tj = 25 °C
RDS(on), Tj = 175 °C
21 mΩ typ, 25 mΩ max, VGS = −10 V, ID = −10.8 A
VGS(th)
−1.5 V min, −2 V typ, −3 V max, ID = −250 µA
Total gate charge
42.7 nC typ, 64 nC max
Ciss / Coss / Crss
2300 pF / 315 pF / 183 pF typ
Rth(j-mb)
1.1 K/W typ, 1.4 K/W max
Rth(j-a)
Not specified in the device datasheet
Description check
The current project description correctly identifies the device as a Nexperia automotive-qualified 40 V P-channel MOSFET in LFPAK56/SOT669 and states the 14 mΩ maximum RDS(on) condition at VGS = −10 V.
Any listing that describes the 64 A current or 110 W dissipation as an ambient-temperature (Ta) rating is incorrect; both are specified with the mounting base at Tmb = 25 °C.
Final assessment
Not suitable for release or normal PCB use in the current state. Device identity and datasheet linkage are correct, but the symbol has unsafe terminal semantics and missing descriptions, while the active footprint has no pads. The part should be corrected so that:
Pins 1–3 are clearly described as Source and treated as one electrical node.
Pin 4 is described as Gate.
The mounting base is represented as Drain without inventing misleading official pin numbers.
Any geometric split Drain pads are guaranteed to share the same net.
A complete SOT669/LFPAK56 footprint is instantiated and verified against the Nexperia reflow land pattern.