# AP1302CSSL00SMGA0-DR (Component)
## Description
Video Processor IC 120-VFBGA (6.5x6.5) Package
Image Signal Processor (ISP) for processing image data from up to 13 MP primary and secondary camera sensors. Supports 13 MP at 30 fps, 1080p at 120 fps, and 720p at 240 fps, with integrated image processing functions including interlaced HDR (iHDR), auto-exposure, auto white balance, autofocus, face detection, and output formats including JPEG, RAW, RGB565, RGB888, and YUV.
#ImageSignalProcessor #ISP #CameraProcessor #13MP #HDR #MIPI #JPEG #RAW #YUV #RGB565 #RGB888 #onsemi
## Component Details
- **Owner:** silicon-yard
- **Created:** 7/9/2026
- **Last Updated:** 7/9/2026
- **Visibility:** Public
- **Package or Case Code:** 120-WFBGA
- **Manufacturer Part Number:** AP1302CSSL00SMGA0-DR
- **License:** https://creativecommons.org/licenses/by/4.0/
- **Datasheet URL:** https://storage.googleapis.com/graviton-electric-symbols/document_assets/user-uploaded/91191e99ec1c0d6d1eaf30813f768cff3cf7327fb15ad6618e7452308e4aa873.pdf
- **Manufacturer Name:** ON Semiconductor
- **Part Type:** Integrated Circuits
- **Symbol Style:** parametric-v1
- **Used in:** 4 projects
## Distributor Pricing (qty 1)
*Pricing shown for quantity 1. For price breaks and other quantities, open in Flux.*
| Distributor | Unit Price (qty 1) | Stock |
|------------|--------------------|-------|
| [Arrow](https://www.arrow.com/en/products/ap1302cssl00smga0-dr/on-semiconductor.html?utm_currency=USD®ion=nac) | N/A | N/A |
| [LCSC](https://www.lcsc.com/product-detail/C606065.html) | $14.7135 | 9 |
| [Mouser](https://www.mouser.com/en/ProductDetail/onsemi/AP1302CSSL00SMGA0-DR?qs=jqKl65nomxZ1a1ah5YFdBQ%3D%3D) | N/A | N/A |
- **Part Type:** Integrated Circuits
- **Sub-Type:** Logic
- **Manufacturer:** ON Semiconductor
- **MPN:** AP1302CSSL00SMGA0-DR
- **Package / Case Code:** VFBGA
- **Pin Count:** 120
- **Logic Function:** AND
## Pins
| Pin | Name | Type |
|-----|------|------|
| A2 | S0_D0_DP | |
| A3 | S0_D1_DP | |
| A4 | S0_CLK_DP | |
| A5 | S0_D2_DP | |
| A6 | S01_D32_DP | |
| A7 | S1_CLK_DP | |
| A8 | S1_D0_DP | |
| A9 | S1_D1_DP | |
| A10 | GPIO[2] | |
| A11 | GPIO[11] | |
| B1 | TESTMODE | |
| B2 | S0_D0_DN | |
| B3 | S0_D1_DN | |
| B4 | S0_CLK_DN | |
| B5 | S0_D2_DN | |
| B6 | S01_D32_DN | |
| B7 | S1_CLK_DN | |
| B8 | S1_D0_DN | |
| B9 | S1_D1_DN | |
| B10 | GPIO[0] | |
| B11 | SIPM_SCL | |
| B12 | GPIO[7] | |
| C1 | IOVDD | |
| C2 | SMIPI_VDD_1 | |
| C3 | SMIPI_VDD_2 | |
| C4 | SMIPI_VSS_1 | |
| C5 | SMIPI_VSS_2 | |
| C6 | SMIPI_VSS_3 | |
| C7 | SMIPI_VSS_4 | |
| C8 | IOVDD_SMISC | |
| C9 | CORE_VDD_1 | |
| C10 | GPIO[1] | |
| C11 | SIPM_SDA | |
| C12 | SIPS_SCL | |
| D1 | CORE_VDD_2 | |
| D2 | SMIPI_VDD_3 | |
| D3 | SMIPI_VDD_4 | |
| D10 | IOVDD_SIPS | |
| D11 | I2C_VSS | |
| D12 | SIPS_SDA | |
| E1 | CORE_VDD_3 | |
| E2 | VSS_1 | |
| E3 | VSS_2 | |
| E5 | VSS_3 | |
| E6 | VSS_4 | |
| E7 | VSS_5 | |
| E8 | VSS_6 | |
| E10 | CORE_VDD_4 | |
| E11 | CORE_VDD_5 | |
| E12 | CORE_VDD_6 | |
| F1 | CORE_VDD_7 | |
| F2 | VSS_7 | |
| F3 | VSS_8 | |
| F5 | VSS_9 | |
| F6 | VSS_10 | |
| F7 | VSS_11 | |
| F8 | VSS_12 | |
| F10 | VSS_13 | |
| F11 | VSS_14 | |
| F12 | CORE_VDD_8 | |
| G1 | CORE_VDD_9 | |
| G2 | VSS_15 | |
| G3 | VSS_16 | |
| G5 | VSS_17 | |
| G6 | VSS_18 | |
| G7 | VSS_19 | |
| G8 | VSS_20 | |
| G10 | VSS_21 | |
| G11 | VSS_22 | |
| G12 | CORE_VDD_10 | |
| H1 | CORE_VDD_11 | |
| H2 | VSS_23 | |
| H3 | VSS_24 | |
| H5 | VSS_25 | |
| H6 | VSS_26 | |
| H7 | VSS_27 | |
| H8 | VSS_28 | |
| H10 | VSS_29 | |
| H11 | VSS_30 | |
| H12 | CORE_VDD_12 | |
| J1 | CORE_VDD_13 | |
| J2 | CORE_VDD_14 | |
| J3 | CORE_VDD_15 | |
| J10 | HMIPI_VDD_1 | |
| J11 | HMIPI_VDD_2 | |
| J12 | GPIO[10] | |
| K1 | STANDBY | |
| K2 | IOVDD_HMISC | |
| K3 | PLL1_VDD | |
| K4 | PLL0_VSS | |
| K5 | VSS_31 | |
| K6 | HMIPI_VSS_1 | |
| K7 | HMIPI_VSS_2 | |
| K8 | HMIPI_VSS_3 | |
| K9 | HMIPI_VDD_3 | |
| K10 | HMIPI_VDD_4 | |
| K11 | IOVDD_GPIO | |
| K12 | GPIO[9] | |
| L1 | RST | |
| L2 | PLL1_VSS | |
| L3 | PLL0_VDD | |
| L4 | GPIO[6] | |
| L5 | VSS_32 | |
| L6 | HMIPI_VSS_4 | |
| L7 | H_CLK_DP | |
| L8 | H_D3_DP | |
| L9 | H_D2_DP | |
| L10 | H_D1_DP | |
| L11 | H_D0_DP | |
| L12 | GPIO[8] | |
| M2 | CLK | |
| M3 | IOVDD_GPIOH | |
| M4 | GPIO[5] | |
| M5 | GPIO[3] | |
| M6 | GPIO[4] | |
| M7 | H_CLK_DN | |
| M8 | H_D3_DN | |
| M9 | H_D2_DN | |
| M10 | H_D1_DN | |
| M11 | H_D0_DN | |
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*Generated from [https://www.flux.ai/silicon-yard/ap1302cssl00smga0-dr](https://www.flux.ai/silicon-yard/ap1302cssl00smga0-dr)*