Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.
I’ll audit the project’s part metadata, fill in any missing official datasheet URL, then compare symbol/footprint/pins against the datasheet and report any mismatches.
Found the existing project datasheet link was for Ag6800, so I located the official Silvertel Ag5300/Ag5324 datasheet and updated a component Datasheet URL reference; now I’m checking pinout and footprint details.
Completed the Ag5324 audit and created the report: Ag5324 Part Audit. Key finding: the current symbol/footprint appears to be for an 18-pin part, while the official Silvertel Ag5324 is a 10-pin SIL PoE+ module; the project-level datasheet URL also points to an Ag6800 datasheet.
Open item:
I updated a component-level Datasheet URL reference, but the project-level datasheet property still appears to need correction to the official Silvertel Ag5300/Ag5324 PDF.
Suggested next steps:
Rebuild the Ag5324 symbol as the correct 10-pin pinout.
Replace the footprint with the verified 10-pin SIL through-hole geometry.
Update project-level metadata to the official datasheet URL.
Reviewed current Flux part/project metadata, schematic symbol terminals, PCB footprint nodes, and official Silvertel datasheet information for Silvertel Ag5324.
Correct official datasheet found: https://silvertel.com/images/datasheets/Ag5300-datasheet-smallest-30W-Power-Over-Ethernet-Plus-Module-PoEplusPD.pdf
Note: I updated a schematic component Datasheet URL reference on VIN+_1 to the official Ag5300/Ag5324 datasheet. The project-level property still appeared to point at the Ag6800 Mouser PDF in the project metadata readout.
Official datasheet summary
Source: Silvertel Ag5300 Power-over-Ethernet Plus Module datasheet, V1.11, April 2024. Datasheet states Ag5300 references apply to Ag5324.
Key Ag5324 specs:
Function: IEEE 802.3af/at PoE+ PD module with isolated DC/DC converter
Package: SIL, through-hole module
Correct pin count: 10 pins
Nominal output: 24 V
Output power: 24 W continuous, 30 W peak at 25 °C, VIN = 52 V
Output current: 1 A continuous
PoE input operating range: 36–57 V
Absolute max DC input: 60 V
Surge input: 80 V max, 1 ms
Operating temperature: −40 °C to +85 °C, derating applies
Isolation: 1500 Vpk impulse test
Peak efficiency: 88%
Minimum load: 100 mA
Recommended output capacitor for 24 V version: 220 µF, 25 V, close to output pins
Official pinout
Table
Datasheet pin
Name
Function
1
VIN+
PoE direct input positive, after external bridge rectifiers
2
VIN−
PoE direct input negative, after external bridge rectifiers
3
AT-DET
IEEE802.3at detect output
4
IC
Internal connection; do not connect
5
IC
Internal connection; do not connect, except optional ESD capacitor note
6
IC
Internal connection; do not connect
7
−VDC
Negative regulated DC output; internally connected to pin 10
8
+VDC
Positive regulated DC output
9
ADJ
Output voltage adjust; leave open for nominal 24 V
10
−VDC
Negative regulated DC output; internally connected to pin 7
Symbol/pin comparison against current project
The current Flux symbol contains 18 separate Terminal components, all using the generic Terminal part UID and all with pin type Unspecified. Current terminal pin numbers/names observed:
Table
Current designator
Current pin number
Datasheet match?
Issue
VIN+_1
1
Partial
Name matches VIN+, but datasheet has only one VIN+ pin.
VIN+_2
2
No
Pin 2 should be VIN−, not VIN+.
IC_1
3
No
Pin 3 should be AT-DET.
IC_2
4
Partial
Pin 4 is IC/DNC.
STATUS
5
No
Pin 5 should be IC/DNC; no STATUS pin in datasheet.
IC_3
6
Partial
Pin 6 is IC/DNC.
IC_4
7
No
Pin 7 should be −VDC.
POH_EN
8
No
Pin 8 should be +VDC; no POH_EN pin in datasheet.
VIN-_1
9
No
Pin 9 should be ADJ.
VIN-_2
10
No
Pin 10 should be −VDC.
OUT1_1
11
No
Datasheet has no pin 11.
OUT1_2
12
No
Datasheet has no pin 12.
0V1_1
13
No
Datasheet has no pin 13.
0V1_2
14
No
Datasheet has no pin 14.
0V2_1
15
No
Datasheet has no pin 15.
0V2_2
16
No
Datasheet has no pin 16.
OUT2_1
17
No
Datasheet has no pin 17.
OUT2_2
18
No
Datasheet has no pin 18.
Footprint comparison against current project
Current layout contains 18 pad nodes plus a default footprint container. The datasheet requires a 10-pin SIL through-hole footprint.
Observed mismatch indicators:
Current footprint/pad count is 18, but the official datasheet pin count is 10.
Current pad designators mirror the incorrect 18-terminal symbol.
The layout silk/outline visible in the flat layout appears roughly 54.76 mm × 37 mm from displayed line coordinates, while the datasheet module body is 57.3 mm long × 14 mm high, with 18.0 mm max depth/thickness in side view. This strongly suggests the footprint geometry is not a verified Ag5324 footprint.
Datasheet footprint data calls for through-hole pins with 2.54 mm pitch, 1.1 ± 0.05 mm recommended PCB holes, separated pin groups, and a large 30.48 ± 0.25 mm isolation gap between pin groups. The current inspection output did not show enough pad geometry detail to confirm these values, but the 18-pad count is already a blocking mismatch.
Key mismatches flagged
Wrong datasheet URL at project level: existing project metadata points to an Ag6800 IEEE802.3bt datasheet, not Ag5324/Ag5300.
Pin count mismatch: current symbol/footprint have 18 terminals/pads; official Ag5324 has 10 pins.
Pin naming/function mismatch: many current pins use names from a different module family or internal naming (STATUS, POH_EN, OUT1/OUT2, duplicated VIN/0V groups) not present in the Ag5324 datasheet.
Pin-number mapping mismatch: only pin 1 is plausibly correct by name; pins 2, 3, 5, 7–18 do not match the official datasheet mapping.
Pin electrical types are unspecified: symbol terminals should be typed more specifically, e.g. VIN+/VIN− as power input, +VDC/−VDC as power output, AT-DET/ADJ as signal/control, IC pins as NC/reserved.
Footprint appears unverified/wrong: 18 pads instead of 10 and outline dimensions do not align with the official Ag5324 package summary.
Recommended corrective action
Rebuild this published part as a 10-pin Silvertel Ag5324 component using the official Ag5300 datasheet:
Update project-level Datasheet URL to the official Silvertel URL.
Replace 18 generic Terminal instances with a single 10-pin symbol or a correct 10-terminal part symbol.
Use the official pin names and pin descriptions from the datasheet table.
Create/replace footprint as a 10-pin through-hole SIL footprint with datasheet mechanical dimensions and correct pin spacing/group gap.
Mark pins 4, 5, 6 as internal connection / do-not-connect.
Ensure pins 7 and 10 are both represented as −VDC and documented as internally connected.