Compact PCB Design for WINO
Thought for 59 sec
- Connected U2:VBAT, U2:VBAT, C13:P1, C10:P1, C14:P1, J4:P1, U5:VBAT, U6:IN, U6:EN to ^VBAT
- Connected U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, U2:GND, C14:P2 to ^GND
- Connected U2:UART_TXD, U1:IO17 to ^SIM_TX
- Connected U2:UART_RXD, U1:IO18 to ^SIM_RX
- Connected U2:SIM_DATA, J3:I/O to ^SIM_DATA
- Connected U2:SIM_CLK, J3:CLK to ^SIM_CLK
- Connected U2:SIM_RST, J3:RST, R6:P2 to ^SIM_RST
- Connected R6:P1 to ^3V3
- Connected U2:VSIM, J3:VCC to ^VSIM
- Connected U2:SIMPRE to ^SIM_DET
- Connected Q1:C, U2:PWRKEY to ^SIM_PWRKEY
- Disconnected J3:I/O, J3:CLK, J3:RST, J3:VCC, Q1:C, R6:P2
nets {
net 3V3 = R6:P1, U1:IO0, U6:OUT, C7:P1, R3:P1, C2:P1, C8:P1, C6:P1, U4:10, U4:9, U4:VDD, U3:V_BCKP, U3:VCC, U1:3V3, M1:3.3V, R4:P1, C12:P1, C5:P1, C4:P1, C3:P1, C1:P1, U1:EN, C11:P1;
net GND = GND:GND, U2 GND - C14 P2:GND, C14:P2, U2:88, U2:87, U2:86, U2:85, U2:84, U2:83, U2:82, U2:81, U2:80, U2:79, U2:78, U2:77, U2:76, U2:73, U2:72, U2:71, U2:67, U2 GND - U2 GND:GND, U2:58, U2:45, U2:44, U2:43, U2:41, U2:39, U2:38, U2:37, U2:35, U2:8, U2:6, U2:2, J3 GND - J4 P2:GND, C4:P2, C3:P2, J3 GND - J3 GND:GND, J3:G6, J3:G2, J3:C5, J3:G4, J3:G1, U3 GND_2 - U3 GND_3:GND, M1:GND, R1 P2 - R2 P2:GND, R1:P2, C9:P2, R2:P2, U6:GND, U3:GND_2, U3:GND_1, C1:P2, J1 SHELL_GND__3 - U1 GND:GND, U1:1, M1:AD0, U4 PGND - U5 VSS:GND, J2:GND_3, C6:P2, C10:P2, J3:G3, C13:P2, J2:GND_1, U1:2, C7:P2, J4:P2, U4:GND, U4:PGND, U5:VSS, U3:GND_3, C2:P2, J1:SHELL_GND__3, J1:SHELL_GND__2, J1:SHELL_GND__1, J1:SHELL_GND, J1:GND__1, C5:P2, U3:GND_4, C11:P2, Q1:E, C8:P2, C12:P2, J2:GND_2, J3:G5, J1:GND;
net I2C_SCL = U1:IO9, R4:P2, M1:SCL, U4:SCL;
net CHG_STAT = U5:STAT;
net VBUS_5V = U5:VIN, C9:P1, J1:VBUS__1, J1:VBUS;
net I2C_SDA = M1:SDA, U1:IO8, U4:SDA, R3:P2;
net MAX_INT = U4:~INT, U1:IO10;
net USB_D+ = J1:DP1, U1:IO20, J1:DP2;
net SIM_TX = U1:IO17, U2:UART_TXD;
net SIM_PWRKEY_CTRL = R5:P2, U1:IO12;
net USB_D- = U1:IO19, J1:DN1, J1:DN2;
net GPS_RX = U1:IO16, U3:TXD1;
net VBAT = U6:EN, U6:IN, U5:VBAT, J4:P1, C14:P1, C10:P1, C13:P1, U2:42, U2:1;
net CHG_PROG = U5:PROG;
net GPS_TX = U1:IO15, U3:RXD1;
net SIM_PWRKEY_BASE = R5:P1, Q1:B;
net SIM_RX = U2:UART_RXD, U1:IO18;
net SIM_DATA = U2:SIM_DATA, J3:I/O;
net SIM_CLK = U2:SIM_CLK, J3:CLK;
net SIM_RST = U2:SIM_RST, R6:P2, J3:RST;
net VSIM = U2:VSIM, J3:VCC;
net SIM_DET = U2:SIMPRE;
net SIM_PWRKEY = Q1:C, U2:PWRKEY;
}
recovering layout selectors and validating remaining blockers...
0:24
Checking 6 design areas.
Reading layout for U2, J3, J1 and 13 more.
Started: recovering layout selectors and validating remaining blockers...
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Project Specification
Design Summary
Status: Draft
Manufacturing target: Prototype
Software / firmware: TBD
Scope
Purpose
WINO is a compact child safety IoT wearable PCB that combines ESP32-S3 control, GSM cellular connectivity, GPS tracking, motion sensing, and pulse oximetry on a rechargeable LiPo-powered board.
In scope
- ESP32-S3 main controller with USB-C programming interface
- SIM800L cellular modem with direct LiPo supply and SIM interface
- NEO-6M GPS receiver with external antenna connector
- Shared I2C sensor bus for MPU-6050 and MAX30102 with 4.7 kOhm pull-ups
- LiPo charger, battery connector, 3.3 V regulation, test points, and compact 2-layer layout targets
Out of scope
- Firmware implementation
- Enclosure and strap mechanical design
System context
This board is the central electronics assembly for a wearable child safety tracker. It manages sensing, location acquisition, and cellular communications from a rechargeable single-cell LiPo battery.
Key interfaces
- USB-C for 5 V input and ESP32-S3 native USB programming
- UART links to SIM800L and NEO-6M
- Shared I2C bus to MPU-6050 and MAX30102
- JST-PH LiPo connector, micro SIM connector, and GPS antenna connector
Block diagram
Diagram
Requirements
Functional
- The board shall support child safety tracking with GPS and GSM subsystems.
- The board shall monitor motion and pulse/SpO2 related optical data through onboard sensors.
- The board shall support USB programming and LiPo battery charging.
Electrical
- Input power: USB-C 5 V for charging and programming, single-cell LiPo battery for mobile operation
- Key rails: direct VBAT for SIM800L, regulated 3.3 V logic rail for ESP32-S3, GPS, and sensors
- Critical interfaces: USB 2.0, UART, shared I2C with 4.7 kOhm pull-ups
- GSM must be physically and electrically isolated from GPS and I2C sensor routing as much as possible on a 2-layer board
Mechanical / environmental
- Board size target: 60 mm x 40 mm
- Layout target: all components on top layer with bottom ground plane
- Form factor: compact wearable electronics assembly
Key constraints
- USB-C CC1 and CC2 each require 5.1 kOhm pull-downs to ground
- I2C SDA and SCL require 4.7 kOhm pull-ups to 3.3 V
- ESP32-S3 antenna must be placed at a board edge with keepout
- SIM800L requires direct battery rail and strong local bulk decoupling
- Bottom layer should remain a continuous ground reference where possible
Dependencies and risks
Dependencies
- Final logic regulator part assignment if AP2112K exact library part remains unavailable
- Firmware GPIO assignment and bring-up validation
Key risks
- GSM burst current noise can degrade GPS and sensor performance if placement and grounding are poor
- 2-layer routing density may constrain ideal RF and power separation
Validation
Success criteria
- All required subsystems are present and correctly connected
- Layout fits inside 60 mm x 40 mm using a 2-layer stackup
- Test points exist for key power and communication nets
Planned checks
- ERC review for floating pins and undriven nets
- Power and pull-up review
- Layout review for placement isolation and airwires
Release-facing notes
Expected deliverables
- Schematic
- PCB layout
- BOM
- Bring-up test access through labeled test points
Special release notes
- Exact AP2112K target is required by plan but currently unavailable as a standalone library part
- Required test points include 3V3, VBAT, GND, I2C, and UART signals
Change notes / open questions
Changes in this revision
- Initial architecture captured
- Core components and first-pass wiring created
Open questions
- Replace provisional regulator implementation with exact AP2112K-compatible library part when available
- Verify any unused modem and GPS pins that should be intentionally left open or tied off
Design Summary
Scope
System context
Requirements
Functional
Electrical
Mechanical / environmental
Key constraints
Dependencies and risks
Validation
Release-facing notes
Change notes / open questions
