# Corresponding Maroon KITT (Component)

## Description

FT2232H USB\-C to GPIO Bridge with Dual LDO Rails and EEPROM on 2\-Layer PCB

## Component Details

- **Owner:** sheikhtanvirsiddiki55
- **Created:** 12/27/2025
- **Last Updated:** 12/27/2025
- **Visibility:** Public
- **Power Trace Width 1\.8 V:** 0\.3mm
- **Crystal Keep\-Out:** 5 mm no\-copper keep\-out region around Y1, C9, and C10
- **Stackup Layers:** 4
- **System Architecture:** \`\`\`mermaid flowchart TD   USB\_C\[USB\-C Connector TYPE\-C\-31\-M\-48\]   POLYFUSE\[USB VBUS Polyfuse\]   LDO\_3V3\[AMS1117\-3\.3 3\.3V Rail\]   LDO\_1V8\[AMS1117\-1\.8 1\.8V Core Rail\]   FT2232H\[FT2232H USB\-to\-GPIO Bridge\]   EEPROM\[24LC02 EEPROM\]   CRYSTAL\[12 MHz Crystal\]   GPIO\_A\[ADBUS\[0\.\.7\] Header\]   GPIO\_B\[BDBUS\[0\.\.7\] Header\]   GND\_PLANE\[Bottom Layer Ground Plane\]   USB\_C \-\-\>\|VBUS\| POLYFUSE   POLYFUSE \-\-\> LDO\_3V3   POLYFUSE \-\-\> LDO\_1V8   LDO\_3V3 \-\-\>\|3\.3V\| FT2232H   LDO\_1V8 \-\-\>\|1\.8V VCORE\| FT2232H   USB\_C \-\-\>\|D\+ / D\- via ESD \+ 22R\| FT2232H   FT2232H \-\-\>\|EECLK / EEDATA\| EEPROM   FT2232H \-\-\>\|OSC Pins\| CRYSTAL   FT2232H \-\-\>\|ADBUS\[0\.\.7\]\| GPIO\_A   FT2232H \-\-\>\|BDBUS\[0\.\.7\]\| GPIO\_B   GND\_PLANE \-\-\- USB\_C   GND\_PLANE \-\-\- FT2232H   GND\_PLANE \-\-\- LDO\_3V3   GND\_PLANE \-\-\- LDO\_1V8   GND\_PLANE \-\-\- EEPROM   GND\_PLANE \-\-\- CRYSTAL   GND\_PLANE \-\-\- GPIO\_A   GND\_PLANE \-\-\- GPIO\_B \`\`\`
- **Controlled Impedance:** 90Ω
- **Ground Plane Layer:** Bottom Layer
- **USB Corridor Width:** 4mm
- **Preferred Stackup:** 4\-layer \(preferred\) with 2\-layer as alternative
- **Stackup:** Standard 4 Layer
- **Power Plane Layer:** Internal Layer 3
- **USB Corridor:** 4 mm no\-copper keep\-out along top edge
- **USB\-to\-GPIO Clearance Rule:** Minimum clearance 5 mm between USB corridor and GPIO header area
- **Internal Layer 3 Assignment:** Power plane
- **USB Differential Net Class \- Controlled Impedance Pair:** 90Ω
- **Power Trace Width 3\.3 V:** 0\.3mm
- **Power Trace Width Rules:** VBUS=0\.5 mm; 3\.3 V=0\.3 mm; 1\.8 V=0\.3 mm
- **Power Island Placement:** F1 → L1 → U2 \(3\.3 V\) and U3 \(1\.8 V\) co\-located in a compact power island region for short, low\-impedance power routing
- **USB Differential Net Class \- Trace Width:** 0\.2mm
- **Internal Layer 2 Assignment:** Ground plane
- **Board Outline:** 80 mm × 40 mm
- **USB Differential Net Class \- Clearance:** 0\.15mm
- **Crystal Oscillator Keep\-Out:** 5 mm routing keep\-out region where no copper pour or traces are allowed around components Y1, C9, and C10
- **Ready for Routing:** true
- **Power Trace Width VBUS:** 0\.5 mm
- **Placement Zones:** USB region: J1 and U5 at the top edge along the 4 mm USB corridor; FT2232H region: U1 centered with R1 and R2 directly adjacent; Crystal loop: Y1 grouped tightly with C9 and C10 within a 5 mm keep\-out; Power island: F1 → L1 → U2 \(3\.3 V\) and U3 \(1\.8 V\) co\-located in a compact power island region for short, low\-impedance power routing; GPIO header: J2 placed at least 5 mm from the USB corridor
- **USB Corridor Role:** High\-speed D\+/D\- routing keep\-out from ground pour and other copper on bottom layer\.
- **USB\_Diff Net Class Impedance:** 90Ω
- **Bottom Layer Ground Pour Net:** GND
- **Ground Pour Configuration:** Bottom layer solid copper pour on GND net with thermal reliefs; maintain 4 mm wide USB D\+/D\- routing corridor along top board edge as copper keep\-out \(no ground pour, no stitching vias\)

- **Mount Type:** PCB
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*Generated from [https://flux\.ai/sheikhtanvirsiddiki55/corresponding\-maroon\-kitt\~41](https://flux.ai/sheikhtanvirsiddiki55/corresponding-maroon-kitt~41)*