Part Datasheet Audit and Updates
Worked for 8 mins 56 sec
Implemented the approved changes and updated Part Datasheet Audit.
Open items:
- ERC delta: 576 → 551 after Batch A support passives, then 551 → 496 after Batch B.
- Spot-checks: LT8610AB RT = 41.2 kΩ → ~1.002 MHz; TPS54540 FB = 1.05 MΩ / 200 kΩ → 5.000 V; TPS259827 RILIM = 211 Ω → ~7.03 A.
- U18/U12/U14/U16/U17 support passives are not wired yet because those refs still need exact/package-correct usable parts.
Suggested next steps:
- Proceed to Batch C: SDMMC1 → eMMC.
- Import/create exact missing power parts.
- Clean up tool-created net portal clutter later.
Thought for 1 min 8 sec
I read the attachment and extracted the new instructions: change TPS54540 FB divider to 10.5 kΩ / 2.00 kΩ, change TPS259827 RILIM to 210 Ω → ~7.06 A, create/import the missing power parts, wire their support passives, and proceed with Batch C eMMC wiring.
Open items:
- I’m blocked now because there are no available ACUs.
- The value table has not yet been updated with the new corrections.
- Missing parts still need create/import: U18, U12, U14, U16, U17.
- Batch C SDMMC1→eMMC has not been wired yet.
- ERC delta after Batch C still needs to be run.
Suggested next steps when ACUs are available:
- Update the support table corrections.
- Create/import missing power parts with “generated — verify pin map against DS” flags.
- Wire support passives and Batch C.
- Run ERC and report the delta.
Create missing parts
Update value table
Wire Batch C
Run ERC delta
Batch A Support Passive Value Table
Date: 2026-07-05
Status: For user verification only — no wiring performed
Assumptions and Flags
- Input/battery maximum for slew/inrush calculations is assumed as 24 V worst-case where the datasheet equation needs an output-voltage magnitude and the project has not yet fixed pack voltage in the file. If the pack maximum is different, dV/dt timing scales directly.
- U18 TPS54540 EN/UVLO requires both turn-on and turn-off thresholds. User specified VIN_on ≈ 8.5 V only; I assumed VIN_off = 7.5 V to compute hysteresis. This row is flagged as requiring confirmation.
- TPS3890 orderable check resolved: use TPS389001DSER or TPS389001DSET adjustable-threshold, open-drain active-low RESET, WSON-6 DSE. The earlier
TPS3890ADRYRstring does not match the official orderable format. - Rows marked multiple valid options are datasheet-supported choices where the exact value depends on startup time, hysteresis, retry behavior, output capacitance, EMI, or derating target.
- The table intentionally excludes standard per-pin 100 nF decoupling enumeration; those are routine but numerous and should be instantiated during the wiring pass.
Computed / Selected Values
Table
| Ref / function | Datasheet source | Target | Raw computed value | Chosen standard value | Resulting actual parameter | Notes / flags |
|---|---|---|---|---|---|---|
| U10/U11 LT8610AB RT | LT8610A/LT8610AB datasheet, Oscillator / RT equation: RT(kΩ)=46.5/fSW(MHz)-5.2; table also lists 41.2 kΩ at 1 MHz | fSW = 1.0 MHz | 41.3 kΩ | 41.2 kΩ E96 | fSW = 46.5/(41.2+5.2)=1.002 MHz | Use one RT resistor per LT8610AB. |
| U10 LT8610AB inductor | LT8610A/LT8610AB typical application / inductor selection guidance | 3.3 V rail, 1 MHz | User target fixed | 4.7 µH shielded, Isat ≥ 5 A | Peak current margin depends on final 3.3 V rail load and VIN range | Multiple valid options: final Isat/DCR should be checked against load budget. |
| U11 LT8610AB inductor | LT8610A/LT8610AB typical application / inductor selection guidance | 5 V rail, 1 MHz | User target fixed | 4.7 µH shielded, Isat ≥ 5 A | Peak current margin depends on final 5 V rail load and VIN range | Multiple valid options: final Isat/DCR should be checked against load budget. |
| U10/U11 LT8610AB TR/SS | LT8610A/LT8610AB TR/SS section: internal 2.2 µA charges cap; FB target follows TR/SS to 0.97 V | CSS = 10 nF requested | tSS = C×0.97 V/2.2 µA = 4.41 ms | 10 nF X7R | tSS ≈ 4.4 ms | Multiple valid options: TR/SS may be changed for startup sequencing. |
| U10 LT8610AB CIN | LT8610A/LT8610AB typical application / input capacitor guidance | 2× 4.7 µF / 25 V | User target fixed | 2× 4.7 µF 25 V X7R | Effective capacitance depends on DC bias | Use close to VIN/GND; add bulk upstream if source impedance requires. |
| U11 LT8610AB CIN | Same as U10 | 2× 4.7 µF / 25 V | User target fixed | 2× 4.7 µF 25 V X7R | Effective capacitance depends on DC bias | Same as U10. |
| U10 LT8610AB COUT | LT8610A/LT8610AB output capacitor / typical application guidance | 2× 47 µF / 6.3 V | User target fixed | 2× 47 µF 6.3 V X7R | Effective capacitance depends on 3.3 V DC bias | Verify derated effective C remains stable for loop. |
| U11 LT8610AB COUT | Same as U10 | 2× 47 µF / 10 V | User target fixed | 2× 47 µF 10 V X7R | Effective capacitance depends on 5 V DC bias | Verify derated effective C remains stable for loop. |
| U10/U11 LT8610AB PG pull-up | LT8610A/LT8610AB PG section: PG is open-drain; typical app uses 100 kΩ pull-up | Pull PG high | Datasheet typical | 100 kΩ E24 to respective logic rail | PG high when FB within ±9% and no fault | U10 PG to P3V3; U11 PG may feed PG_5V per current plan. |
| U10/U11 LT8610AB BIAS | LT8610A/LT8610AB BIAS section: for outputs ≥3.3 V, tie BIAS to VOUT | Improve efficiency | Datasheet recommendation | Direct tie to VOUT | BIAS supplied when VBIAS > about 3.1 V | Already high-level tied in Batch A. |
| U18 TPS54540 RT | TPS54540 datasheet RT/CLK section: RT(kΩ)=101756/fSW(kHz)^1.008; electrical table lists 200 kΩ ≈ 500 kHz typ | fSW ≈ 500 kHz | 193.64 kΩ | 196 kΩ E96 | fSW ≈ 494 kHz | Alternative: 200 kΩ gives ≈484 kHz but matches table typical. Multiple valid options. |
| U18 TPS54540 FB top | TPS54540 datasheet FB equation: VOUT=0.8×(1+RHS/RLS) | VOUT = 5.0 V, RLS = 200 kΩ | RHS = 1.050 MΩ | 1.05 MΩ E96 | VOUT = 5.000 V nominal | 1% resistors. RLS=200 kΩ is a common datasheet-style choice. |
| U18 TPS54540 FB bottom | Same FB equation | VOUT = 5.0 V | Chosen base value | 200 kΩ E24/E96 | With 1.05 MΩ top, VOUT=5.000 V | Multiple valid options: divider current vs noise tradeoff. |
| U18 TPS54540 EN/UVLO top | TPS54540 datasheet section 7.3.7 Enable/UVLO: RUVLO1=(VSTART-VSTOP)/IHYS; IHYS≈3.4 µA | VIN_on=8.5 V, assumed VIN_off=7.5 V | 294.1 kΩ | 294 kΩ E96 | With Rbottom=46.1 kΩ, VIN_on≈8.500 V, VIN_off≈7.501 V | Flag: VIN_off assumption must be confirmed. |
| U18 TPS54540 EN/UVLO bottom | TPS54540 section 7.3.7: RUVLO2=VENA/(((VSTART−VENA)/RUVLO1)+I1); VENA≈1.2 V, I1≈1.2 µA | VIN_on=8.5 V | 46.12 kΩ | 46.1 kΩ E96 | VIN_on≈8.500 V, VIN_off≈7.501 V | Multiple valid options if different hysteresis is desired. |
| U18 TPS54540 soft-start | TPS54540 datasheet soft-start: internal digital SS ramps in 1024 cycles; tSS(ms)=1024/fSW(kHz) | fSW≈500 kHz | 2.048 ms | No external SS cap for TPS54540 | tSS≈2.07 ms at 494 kHz | Confirmed by user: drop external SS cap. |
| U18 TPS54540 BOOT cap | TPS54540 datasheet typical application / bootstrap guidance | BOOT to PH/SW | Datasheet typical | 0.1 µF X7R | Bootstrap gate-drive cap | Must connect BOOT to PH/SW, not GND. |
| U18 TPS54540 inductor | TPS54540 datasheet output inductor selection, Eq. 28: LO(min)=((VINmax−VOUT)×VOUT)/(IOUT×KIND×VINmax×fSW); KIND≈0.3 for ceramics | 5 V LED rail, 500 kHz class | User target fixed | 8.2 µH, Isat ≥ 6 A | Ripple/peak depend on final VINmax and LED load | Multiple valid options; user target is acceptable pending load budget. |
| U18 TPS54540 COUT | TPS54540 output cap guidance / user target | LED 5 V rail | User target fixed | 3× 47 µF 10 V X7R + local bulk bank | Effective capacitance depends on DC bias and local bulk | Check downstream bulk after eFuse remains ≤500 µF total. |
| U13 TPS259827 RILIM | TPS25982 datasheet current-limit equation: RILIM(Ω)=1460/(IILIM(A)−0.11) | IILIM = 7.0 A | 211.9 Ω | 210 Ω E24 or 211 Ω E96 | 210 Ω → 7.06 A; 211 Ω → 7.03 A | Choose 211 Ω E96 if available; 210 Ω E24 is also acceptable. |
| U13 TPS259827 dVdt cap | TPS25982 datasheet dVdt equations: SR(V/ms)=IINRUSH(mA)/COUT(µF), CdVdt(pF)=4600/SR; for voltage ramp, SR≈VOUT/t | ~5 ms output rise at assumed 24 V | SR=24/5=4.8 V/ms; CdVdt=958 pF | 1.0 nF C0G/X7R | SR≈4.6 V/ms; 24 V rise≈5.22 ms | Flag: actual rise time scales with pack voltage and downstream capacitance. |
| U13 TPS259827 RETRY_DLY cap | TPS25982 datasheet retry delay equation/example: CRETRY_DLY(pF)=tRETRY_DLY(µs)/46.83−4 | 100 ms retry delay | 2131 pF | 2.2 nF E24 | tRETRY_DLY≈103.2 ms | This is the actual retry-delay pin. |
| U13 TPS259827 ITIMER cap | TPS25982 datasheet ITIMER equation/example: CITIMER(nF)=tITIMER(ms)/0.47 | 2–5 ms transient overcurrent blanking | For 2 ms: 4.26 nF; for 5 ms: 10.64 nF | 4.7 nF E24 | tITIMER≈2.21 ms | Confirmed by user: use short blanking to ride through transients. |
| U13 TPS259827 NRETRY / auto-retry mode | TPS25982 datasheet fault response table | Auto-retry indefinitely with finite delay | Pin-strap, no equation if infinite retry | NRETRY short to GND; RETRY_DLY cap to GND | Infinite retries with finite delay | Multiple valid options: finite retry uses CNRETRY equation and quantized 4/16/64/256/1024 retries. |
| U13 TPS259827 FLT pull-up | TPS25982 open-drain / fault output usage | Optional FLT | Datasheet typical/open drain style | 100 kΩ to logic rail, or leave NC | FLT available if populated; no effect if NC | User says leave unconnected optional. |
| U13 TPS259827 IMON | TPS25982 IMON load monitor pin | Not used | User target | Mark no-connect / leave unused per datasheet if allowed | INA226 covers current | Verify datasheet unused-pin guidance before NC. |
| U12 LM74722-Q1 boost L | LM74722-Q1 datasheet section 9.2.2.2 Boost Converter Components | Integrated boost regulator | Datasheet value | 100 µH, Isat >175 mA | Supports CAP/LX boost drive | Typical app uses Coilcraft XPL2010-104ML class. |
| U12 LM74722-Q1 C2 | LM74722-Q1 datasheet section 9.2.2.2 | CAP to C/FET drain node | Minimum 1 µF | 1 µF X7R | Boost flying/storage cap | Place per datasheet close to CAP/C. |
| U12 LM74722-Q1 C3 | LM74722-Q1 datasheet section 9.2.2.2 | C node to GND | Minimum 1 µF | 1 µF X7R | Boost output/reference cap | Typical app value. |
| U12 LM74722-Q1 D2 clamp | LM74722-Q1 Figure 9-1 typical application | CAP/boost clamp | Datasheet typical | 18 V diode / TVS per typical app | Protects boost/gate network | Verify exact diode type/package during part selection. |
| U12 LM74722-Q1 gate network | LM74722-Q1 Figure 9-1 typical application | Back-to-back MOSFET gate drive | Datasheet typical | Common-source PSMN1R5-40YLC FET pair; include typical R/C around gate/PD per figure | Ideal-diode / reverse protection | Multiple valid options: final FET and gate damping depend on current/thermal/load dump requirements. |
| U14 MAX16151 VCC bypass | MAX16151 datasheet typical application | VCC local bypass | Datasheet typical | 100 nF X7R | VCC decoupling | Place close to VCC/GND. |
| U15 TPS70933 CIN | TPS709 datasheet design procedure / capacitor section | Input filtering | Datasheet design example | 1.0 µF 25 V X7R | Input transient/noise filtering | User requested 1 µF; matches datasheet input example. |
| U15 TPS70933 COUT | TPS709 datasheet: stable with effective output capacitance ≥2.0 µF for low VOUT; design example uses 2.2 µF 10 V X7R | Output stability | Datasheet minimum effective ≥2.0 µF | 2.2 µF 10 V X7R | Meets stability better than 1 µF nominal | Flag: user requested 1 µF, but datasheet points to ≥2.0 µF effective / 2.2 µF nominal. |
| U16 TPS389001 divider top | TPS3890 adjustable-threshold equation: VITx(MON)=VITx×(1+R1/R2); VITN=1.15 V for TPS389001 adjustable | 4.5 V falling threshold; Rtop≈1 MΩ requested | 1.000 MΩ selected base | 1.00 MΩ E96 | With Rbot=340 kΩ, threshold≈4.532 V | Exact 4.5 V needs Rbot≈343.3 kΩ; 340 kΩ gives conservative-high trip. |
| U16 TPS389001 divider bottom | Same equation | 4.5 V falling threshold | 343.3 kΩ | 340 kΩ E96 | 340 kΩ → 4.532 V falling threshold | Confirmed family supports adjustable threshold/open-drain active-low RESET. |
| U16 TPS3890 CT | TPS3890 CT delay equation: tPD(r)(sec)=CCT(µF)×1.07+25 µs | ~10 ms delay | CCT=(0.010−0.000025)/1.07=0.00932 µF = 9.32 nF | 9.31 nF E96, or 10 nF E12 | 9.31 nF → 9.99 ms; 10 nF → 10.73 ms | Multiple valid options. |
| U17 TPS3839K33 bypass | TPS3839 datasheet typical application / bypass guidance | Fixed 2.93 V supervisor on 3.3 V rail | Datasheet typical | 100 nF X7R | Local VDD bypass | RESET delay is internal ~200 ms; RESET to ESP32 EN. |
| U8 INA226 bypass | INA226 datasheet typical application / supply bypass | VS local bypass | Datasheet typical | 100 nF X7R | VS decoupling | Place close to VS/GND. |
| U8 INA226 IN+ filter R | INA226 datasheet filtering section: RFILTER ≤10 Ω, lowest possible; tested with 10 Ω | Input noise filter | ≤10 Ω | 10 Ω 1% | Differential input filter with CFILTER | Use one series resistor in each IN path. |
| U8 INA226 IN− filter R | Same as above | Input noise filter | ≤10 Ω | 10 Ω 1% | Differential input filter with CFILTER | Match IN+ resistor. |
| U8 INA226 input filter C | INA226 datasheet filtering section: CFILTER = 0.1 µF to 1 µF ceramic across inputs | Input noise filter | Datasheet range | 100 nF X7R | Input low-pass with 10 Ω+10 Ω source resistance | Multiple valid options: 0.1–1 µF supported; bandwidth depends on value. |
Items Requiring Confirmation Before Wiring
- Resolved: TPS54540 has internal soft-start; no external SS capacitor.
- Resolved: TPS54540 UVLO uses Von=8.5 V and Voff=7.5 V.
- Resolved: TPS259827 ITIMER uses 4.7 nF for ~2.21 ms transient blanking; RETRY_DLY is separate.
- Resolved: use TPS389001DSER/DSET adjustable-threshold open-drain part, not TPS3890ADRYR.
- Resolved: TPS70933 COUT uses 2.2 µF X7R minimum.
- Still open: LM74722 U12 external FET/current path should be reviewed against input current/load-dump requirements before layout.
Assumptions and Flags
Computed / Selected Values
Items Requiring Confirmation Before Wiring