BQ25185 Charger Topology

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Leeré el adjunto y ejecutaré únicamente el alcance autorizado sobre el proyecto BENCH_ONLY actual.

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Aplicaré únicamente la corrección autorizada de U9: crearé C20 dedicado en VDDR, conservaré C15 y el modo LDO interno, colocaré sólo C20 junto a U9 y verificaré conectividad/ERC con capturas enfocadas.

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C20 quedó añadido y colocado junto a U9 sin tocar otros bloques. Estoy cerrando la verificación independiente de nets, footprint y ERC.

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Corrección U9 aplicada y guardada:
  • C20: Murata GRM21BZ71A226ME15L, LCSC C907991, 22 µF, 10 V, X7R, 0805
  • C20.1 → CC1354_VDDR
  • C20.2 → DGND_SERVICE
  • C15 permanece entre RX_3V3 y DGND_SERVICE
  • U9 permanece en modo LDO interno, con DCDC_SW NC
  • C20 fue colocado junto a U9; no se movieron otros componentes
ERC: 9 hallazgos preexistentes e intencionales — U10 NC, cuatro nets RF abiertas y cuatro nets LM5069 abiertas. C20 no introdujo errores nuevos. Las capturas enfocadas de esquema y PCB se muestran arriba.
BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION.
Fix ERC blockers
Update sourcing notes
Review C20 placement
Arrange U9 block
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Schematic

Layout

3D View

Final Schematic Correctness Review
Status: BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION
Visible progress: 75% logical shadow definition / 0% fabrication release
Review date: 2026-07-28
This review reflects the current schematic after the exact K1–K3 and U10 replacements and the U8 power-save/source-placeholder correction.
Confirmed current corrections

Table

BlockConfirmed stateResult
BQ25185AIRTAG_CHG_SYS contains U3.SYS and C5.1 only; U3.CE remains on AIRTAG_PACK_NEGCorrect
K1–K3Exact G5LE-14 5VDC entries; pin 1 on RX_5V, pin 2 on channel coil-negative net, pins 3–5 external/no-connectCorrect for official Omron pinout
U10Exact MCP41HV51-503E/ST; SPI nets mapped to SCK/CS/SDI/SDO, WLAT low, SHDN controlled, analog terminals openLogically correct BENCH_ONLY
U10 pins 8/9Flux library labels are swapped relative to Microchip. Both physical pads are grounded, satisfying DGND and the recommendation for NCElectrically acceptable; justified library ERC finding
U8 PS/SYNCConnected to DGND_SERVICEPower-save mode selected
U8 input sourceV_CELL_PLACEHOLDER drives AIRTAG_CELL_POS from a schematic-only 1S placeholder connected between CELL_POS and CELL_NEGClears ERC without selecting a real battery; excluded from PCB/BOM/PnP
TPS63030VIN/VINA/EN on AIRTAG_CELL_POS; PS/SYNC low; L1/L2, VOUT and FB memberships preservedFocused block check clean
Correct only as a BENCH_ONLY shadow schematic
  • V_CELL_PLACEHOLDER is not a purchasable battery and does not define chemistry, capacity, protection or permitted charge current.
  • LM5069 UVLO, OVLO, TIMER and PWR remain intentionally open pending real input/load/SOA requirements.
  • Four U9 RF ports remain intentionally open pending antenna, matching, stackup and compliance decisions.
  • U10 V+, V− and potentiometer terminals remain on the explicit analog-open net.
  • BQ29700 COUT/DOUT and the final protection-FET implementation remain unresolved.
  • J1, U1, L1, L2 and generic-passive manufacturing qualification remain open.
  • Q2/Q3 remain DNP/BENCH_ONLY; relay contacts remain external and unconnected.
Full ERC disposition
Total findings: 9
Justified library finding — 1
  • U10:NC connected: caused by swapped pin 8/9 metadata in the exact Flux entry. Both physical pads are intentionally grounded and the disposition is recorded separately.
Intentional BENCH_ONLY open nets — 8
  • LM5069: LM5069_UVLO_OPEN, LM5069_OVLO_OPEN, LM5069_TIMER_OPEN, LM5069_PWRSET_OPEN.
  • RF: RF915_P_OPEN, RF915_N_OPEN, RF_PA20_P_OPEN, RF_PA20_N_OPEN.
New real ERC errors
  • None. U8 PS/SYNC and the undriven AIRTAG_CELL_POS error are resolved.
Final verdict
LOGICALLY_CONSISTENT_BENCH_ONLY
  1. The previously identified U10, relay and U8 electrical errors have been corrected.
  2. The TPS63030 block now has a defined power-save state and an explicit non-manufacturing source placeholder.
  3. Current ERC contains no new unintended connectivity error.
  4. The U10 NC finding is a documented library-metadata defect with an electrically acceptable grounding disposition.
  5. Eight remaining single-pin nets are deliberate BENCH_ONLY markers for unresolved LM5069 and RF design work.
  6. Battery selection, protection completion, RF, LM5069 settings and manufacturing qualification remain incomplete.
  7. The schematic is logically consistent only as a shadow design and must not be energized or released to PCB/fabrication.
  8. BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION.

  • Confirmed current corrections

  • Correct only as a BENCH_ONLY shadow schematic

  • Full ERC disposition

  • Justified library finding — 1

  • Intentional BENCH_ONLY open nets — 8

  • New real ERC errors

  • Final verdict