BQ25185 Charger Topology
Thought for 49 sec
Aplicaré únicamente la corrección autorizada de U9: crearé C20 dedicado en VDDR, conservaré C15 y el modo LDO interno, colocaré sólo C20 junto a U9 y verificaré conectividad/ERC con capturas enfocadas.
Worked for 10 mins 55 sec
C20 quedó añadido y colocado junto a U9 sin tocar otros bloques. Estoy cerrando la verificación independiente de nets, footprint y ERC.
Worked for 2 mins 1 sec
Corrección U9 aplicada y guardada:
- C20: Murata
GRM21BZ71A226ME15L, LCSCC907991, 22 µF, 10 V, X7R, 0805 - C20.1 →
CC1354_VDDR - C20.2 →
DGND_SERVICE - C15 permanece entre
RX_3V3yDGND_SERVICE - U9 permanece en modo LDO interno, con
DCDC_SWNC - C20 fue colocado junto a U9; no se movieron otros componentes
ERC: 9 hallazgos preexistentes e intencionales — U10 NC, cuatro nets RF abiertas y cuatro nets LM5069 abiertas. C20 no introdujo errores nuevos. Las capturas enfocadas de esquema y PCB se muestran arriba.
BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION.
Fix ERC blockers
Update sourcing notes
Review C20 placement
Arrange U9 block
Refine this doc
Ask about this doc
Brand NewDay — Flux 80 Percent Completion Plan
Mandatory state: BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION
Scope: Engineering closure backlog only. No schematic, PCB, nets, BOM, libraries, placement, routing, or manufacturing outputs were modified or generated.
Scope: Engineering closure backlog only. No schematic, PCB, nets, BOM, libraries, placement, routing, or manufacturing outputs were modified or generated.
Visible Completion Scale
Text
0% 10 20 30 40 50 60 70 80 90 100% |-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| ████████████████████████████████████████░░░░░░░░░░ 80%
Current engineering-documentation estimate: 80%.
This percentage means the architecture, logical netlist and reconstruction documentation are substantially defined. It does not mean the PCB is 80% ready for fabrication or energization.
This percentage means the architecture, logical netlist and reconstruction documentation are substantially defined. It does not mean the PCB is 80% ready for fabrication or energization.
1. COMPLETO EN FLUX
1.1 Architecture and Functional Blocks — 100%
- USB-C service, ESD and CP2102N USB-UART architecture documented.
- BQ25185 charger/power-path, BQ29700 protection and TPS63030 buck-boost blocks documented.
- LM5069 protected HV entry, Q1 pass MOSFET, LM5164 5 V buck and TPS7A2033 3.3 V rail documented.
- CC1354P106 controller/RF interface, UART, SPI, reset and power domains documented.
- MCP41HV51 intended SPI digital-potentiometer block documented with corrected official pinout.
- Three relay driver channels and DNP Q2/Q3 experimental paths documented.
1.2 Logical Nets and Pin Mapping — 95%
Completed:
- 61 current Flux nets inventoried.
- Pin-to-net tables generated for every block.
- AIRTAG_CHG_SYS correction verified: U3.SYS + C5.1 only.
- U3.CE verified on AIRTAG_PACK_NEG/GND, never SYS.
- UART, SPI-intent, power, feedback and relay-drive nets documented.
- Open RF, LM5069 control and external interface nets labelled.
Remaining logical corrections are known but intentionally not applied:
- Exact U10 SPI symbol must replace the incompatible MCP45HV proxy.
- Exact relay pin mapping must use coil pins 2/5 and contacts 1/3/4.
- U8 PS/SYNC policy awaits implementation approval.
1.3 Verified Components and Safe Proxies — 90%
Exact symbol/footprint verification completed for:
- U2 CP2102N-A02-GQFN28
- U3 BQ25185DLHR
- U4 BQ29700DSER
- U5 TPS7A2033PDBVR
- U7 LM5164DDAR
- Q1 CSD19536KTT
- Q2/Q3 CSD16406Q3, retained DNP
Pin/package-safe proxies documented for:
- U6 LM5069MMX-1/NOPB → LM5069MM-1/NOPB
- U8 TPS63030DSK → TPS63030DSKR
- U9 CC1352P1F3RGZR symbol/footprint → CC1354P106T0RGZR
- Q4/Q5/Q6 CSD13380F3T → CSD13380F3
- D1/D2/D3 PMEG2010AEB,115 → PMEG2010AEB
1.4 Documentation — 100%
Available project files include:
- Project Specification and Shadow Build Report.
- Phase 2 engineering decisions.
- Component Qualification Manifest.
- Phase 2.2 Proxy Pin Qualification Report.
- Phase 2.3 exact-entry creation specification/blocker report.
- EasyEDA Manual Reconstruction Manifest.
- Component and Footprint Qualification Matrix covering all 69 designators.
2. DECISIONES QUE EL USUARIO DEBE DEFINIR
2.1 Battery System — 35% Closed
Table
| Required decision | Exact missing data | Why it affects the circuit | Must not be invented | What Flux can complete without it |
|---|---|---|---|---|
| Chemistry | Li-ion, Li-poly or another specific 1S chemistry; maximum charge voltage | R6=24 kΩ currently implies 4.2 V regulation. Wrong chemistry/voltage can damage the cell | Do not assume all 1S cells accept 4.2 V | Preserve charger topology, SYS/CE correction and programming-net documentation |
| Capacity | Battery capacity in mAh and manufacturer MPN | Determines suitable C-rate and charge time | Do not infer capacity from product type or enclosure | Maintain current R7 calculation as provisional only |
| Charge current | Permitted normal and maximum charge current | R7=21.5 kΩ gives approximately 14 mA typical | Do not increase current to shorten charging without cell data | Document ICHG formula and candidate RSET values |
| Protection arrangement | Protected cell, bare cell, external FETs and connector arrangement | U4 COUT/DOUT are currently open; protection path is incomplete | Do not assume protection is built into the battery | Keep BQ29700 pins and open protection interfaces documented |
| Battery connector | MPN, polarity, current rating and mechanical access | Defines interface, ERC and physical layout | Do not select a connector by convenience | Reserve labelled AIRTAG_CELL_POS/NEG interfaces in documentation |
2.2 High-Voltage Input / LM5069 — 25% Closed
Table
| Required decision | Exact missing data | Why it affects the circuit | Must not be invented | What Flux can complete without it |
|---|---|---|---|---|
| VIN minimum/nominal/maximum | Full operating and transient range | Sets UVLO/OVLO and voltage ratings | Do not assume 12 V, 24 V, 48 V or automotive range | Preserve VIN_RAW/VIN_SENSE/VIN_PROTECTED topology |
| Load current | Continuous, peak, startup and fault current | Determines R9 suitability, Q1 SOA, buck sizing and copper | Do not use regulator headline current as system current | Maintain equations and component roles |
| Input fuse/protection | Fuse type/rating, surge, reverse polarity and transient requirements | Controls fire/fault risk and upstream protection | Do not invent a fuse rating without load/transient data | Document a placeholder protection requirement only |
| UVLO thresholds | VUVL and VUVH | Determines valid startup/shutdown window | Do not choose thresholds from a generic reference design | Keep LM5069_UVLO_OPEN and TI equations documented |
| OVLO thresholds | VOVL and VOVH | Defines overvoltage shutdown | Do not disable OVLO or choose values without maximum safe voltage | Keep LM5069_OVLO_OPEN and TI equations documented |
| TIMER | Allowed startup time, fault timeout, output capacitance/inrush | Sets fault response and MOSFET stress | Do not copy TI example 150 nF without startup/SOA analysis | Keep tFAULT/tINSERT equations documented |
| PWR limit | Q1 allowed PLIM versus VDS and temperature | Prevents MOSFET SOA failure | Do not derive from room-temperature current rating alone | Keep RPWR equation and Q1 SOA requirement documented |
2.3 U10 Analog Function — 20% Closed
Table
| Required decision | Exact missing data | Why it affects the circuit | Must not be invented | What Flux can complete without it |
|---|---|---|---|---|
| V+ | Positive analog terminal supply/limit | Defines allowed potentiometer terminal range | Do not tie V+ to RX_3V3 or another rail without analog requirements | Preserve exact MCP41HV51 pinout and leave V+ open |
| V− | Negative/low analog supply | Defines bipolar or unipolar operation | Do not assume V− is DGND | Preserve V− as an open analog interface |
| P0A / P0B | End-terminal signals and voltage/current ranges | Determines what resistance network is controlled | Do not connect to a machine/control signal by name alone | Preserve open labelled terminals |
| P0W | Wiper destination, load impedance and expected range | Defines circuit function and safety | Do not invent a feedback/control destination | Preserve wiper as open |
| Analog function | Gain, trim, bias, threshold or emulation purpose | Determines whether MCP41HV51 is the correct topology/value | Do not assume it is a generic 50 kΩ volume/control pot | Complete SPI/control-side documentation only |
2.4 RF System — 15% Closed
Table
| Required decision | Exact missing data | Why it affects the circuit | Must not be invented | What Flux can complete without it |
|---|---|---|---|---|
| Operating band(s) | Sub-1 GHz frequency/region and whether 2.4 GHz is used | Selects RF port, matching and antenna | Do not assume 915 MHz globally | Keep RF port pins labelled/open |
| Antenna | Exact antenna MPN or approved reference geometry | Governs performance and certification | Do not draw a generic PCB antenna | Preserve RF interface nets only |
| Matching network | Topology/values derived from antenna/reference layout | Required for impedance and power transfer | Do not copy matching values across layouts | Reserve an unimplemented matching requirement |
| PCB stackup | Manufacturer dielectric, layer distances, copper weight | Determines RF impedance and feed geometry | Do not claim controlled impedance without stackup | Keep current 4-layer concept labelled unqualified |
| Compliance target | FCC/CE/RED region and module/product strategy | Affects band, antenna gain and test plan | Do not claim certification from schematic alone | Maintain regulatory documentation skeleton |
2.5 Relay Load Interfaces — 20% Closed
Table
| Required decision | Exact missing data | Why it affects the circuit | Must not be invented | What Flux can complete without it |
|---|---|---|---|---|
| Load voltage/current/type | AC/DC, nominal, transient, inductive/resistive | Determines contact rating, arc suppression and clearances | Do not assume low-voltage DC because the coil is 5 V | Keep contacts external/open |
| Connector | Exact MPN, pitch, current/voltage rating | Determines mechanical and safety interface | Do not create a generic machine connector | Document connector requirement only |
| Contact fuse | Fuse type/rating and placement | Protects relay contacts and wiring | Do not use coil current to size contact fuse | Keep fuse requirement open |
| Isolation/clearance | Required creepage, clearance and domain separation | Determines board partition and routing | Do not use default digital clearances | Retain BENCH_ONLY and no load nets |
| Snubber/flyback at load | Load-specific suppression method | Controls arcing/EMI/contact life | Do not add RC/MOV/TVS without load data | Coil-side flyback documentation remains complete |
2.6 L2 Buck-Boost Inductor — 30% Closed
| Required decision | Exact missing data | Why it affects the circuit | Must not be invented | What Flux can complete without it |
| Exact MPN | Manufacturer and orderable 2.2 µH 0805 part | Needed for real footprint and sourcing | Do not treat any 0805 2.2 µH part as equivalent | Keep generic two-pin symbol/value |
| Isat | Required minimum saturation current | Prevents current-limit saturation | Do not derive from inductance/package alone | Keep TPS63030 switching topology documented |
| DCR | Maximum acceptable series resistance | Affects efficiency, drop and thermal rise | Do not use a typical internet value | Record DCR as a selection criterion |
| Irms | Continuous RMS current at allowed temperature rise | Determines thermal suitability | Do not equate Isat with Irms | Record Irms/temperature-rise requirement |
| Tolerance/frequency behavior | Inductance tolerance and bias curve | Affects converter stability/performance | Do not specify only nominal 2.2 µH | Require manufacturer curves before PCB release |
3. BLOQUEOS DE LIBRERÍA PARA EASYEDA
3.1 Critical Exact Components
Table
| Reference | Required exact entry | Current state | Closure action |
|---|---|---|---|
| J1 | DX07S016JA3R1500 / C3197625 | JA1 is UNSAFE_PROXY; exact JA3 entry absent (J1_LIBRARY_GAP) | Create/import exact footprint using JAE SJ122205 only; validate pads, pin numbering, shell tabs, holes/slots, cutout, board-edge datum, orientation and permitted PCB thickness; compare 1:1 with EasyEDA C3197625. SJ122206 is packaging only |
| U1 | TPD4E05U06DQAR | Current part is TPD4E02B04DQAR; same pin/package geometry but different ESD silicon/spec | Replace with exact TI MPN and revalidate protection requirements |
| U10 | MCP41HV51-503E/ST | Current MCP45HV proxy is I²C and pin-incompatible | Create exact SPI symbol; use official pin mapping; bind TSSOP-14 footprint |
| K1/K2/K3 | G5LE-14-DC5 | Current proxy pin interpretation is incorrect | Create exact Omron relay symbol/footprint; coil pins 2/5, contacts 1/3/4 |
| L1 | MSS1246T-683MLB | Generic symbol and incorrect small footprint | Create exact 12×12 mm Coilcraft footprint |
| L2 | Exact 2.2 µH MPN TBD | Generic 0805 placeholder | Select part after Isat/DCR/Irms definition |
3.2 Passive MPN Closure
All R1–R25 and C1–C19 currently use generic value/package components. Their logical symbols are sufficient for schematic reconstruction, but exact purchasable MPNs must be selected for:
- resistance/capacitance tolerance;
- voltage and power rating;
- capacitor dielectric, ESR and DC-bias derating;
- resistor pulse/TCR requirements;
- manufacturer-specific land-pattern confirmation;
- sourcing and lifecycle.
These generic passives are not fabrication-qualified.
4. PAQUETE DE EXPORTACIÓN FINAL DE FLUX
This section defines the required closure package. It does not claim these files were generated in this phase.
Table
| Deliverable | Intended format | Current readiness | Export gate |
|---|---|---|---|
| Schematic Netlist | .edif | Logical netlist documented; contains known proxy mismatches in current Flux state | Export only after deciding whether the file should represent current Flux proxies or corrected EasyEDA mapping |
| Bill of Materials | .zip | Current BOM exists but includes proxies and generic passives | Export after exact MPN closure or clearly mark preliminary/BENCH_ONLY |
| Flux Project | .flx | Current project exists | Export as archival BENCH_ONLY snapshot; not manufacturing release |
| Qualification Matrix | Project document / downloadable report | Complete | Include current Component and Footprint Qualification Matrix |
| EasyEDA Manifest | Project document / downloadable report | Complete | Include EasyEDA Manual Reconstruction Manifest |
Recommended Package Naming
Text
Brand_NewDay_Flux_BENCH_ONLY_<date>/ ├── Brand_NewDay_Schematic_Netlist.edif ├── Brand_NewDay_BOM_Preliminary.zip ├── Brand_NewDay_Shadow_Project.flx ├── Component_and_Footprint_Qualification_Matrix.pdf-or-md └── EasyEDA_Manual_Reconstruction_Manifest.pdf-or-md
Every exported artifact must be visibly marked:
BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION
Closure Sequence from 80% to 100%
Table
| Progress | Required milestone | Owner |
|---|---|---|
| 80% | Current architecture, netlist, qualification and reconstruction documentation | Flux complete |
| 84% | User supplies battery definition and charger approval | User |
| 88% | User supplies HV input/load/fault limits; LM5069 values calculated | User + engineering |
| 91% | U10 analog purpose and terminal voltages defined | User |
| 94% | RF band/antenna/matching/stackup defined | User + RF engineering |
| 96% | Relay loads/connectors/fuses/isolation defined | User + safety engineering |
| 97% | L2 and all passive exact MPNs selected | Engineering/sourcing |
| 98% | Exact EasyEDA/Flux libraries created and pin/pad verified | Library engineering |
| 99% | Corrected schematic ERC and PCB DRC/DFM review complete | Engineering |
| 100% | Controlled export package approved for intended use | User + responsible engineer/manufacturer |
Stop Point
The project remains at an 80% engineering-documentation stage and 0% fabrication release. No fabrication-ready claim is permitted until every decision and library/DFM gate above is closed.
Brand NewDay — Flux 80 Percent Completion Plan
Visible Completion Scale
1. COMPLETO EN FLUX
1.1 Architecture and Functional Blocks — 100%
1.2 Logical Nets and Pin Mapping — 95%
1.3 Verified Components and Safe Proxies — 90%
1.4 Documentation — 100%
2. DECISIONES QUE EL USUARIO DEBE DEFINIR
2.1 Battery System — 35% Closed
2.2 High-Voltage Input / LM5069 — 25% Closed
2.3 U10 Analog Function — 20% Closed
2.4 RF System — 15% Closed
2.5 Relay Load Interfaces — 20% Closed
2.6 L2 Buck-Boost Inductor — 30% Closed
3. BLOQUEOS DE LIBRERÍA PARA EASYEDA
3.1 Critical Exact Components
3.2 Passive MPN Closure
4. PAQUETE DE EXPORTACIÓN FINAL DE FLUX
Recommended Package Naming
Closure Sequence from 80% to 100%
Stop Point
