BQ25185 Charger Topology
Thought for 9 sec
Leeré ambos adjuntos, reconciliaré sus instrucciones y aplicaré únicamente el alcance autorizado al proyecto BENCH_ONLY actual.
Thought for 46 sec
Ambos adjuntos son idénticos. Revisaré exclusivamente los 21 MPN faltantes, aprobaré sólo pasivos estándar con requisitos cerrados y aplicaré únicamente metadatos MPN/LCSC; las dependencias de LM5069, CC1354 y convertidores permanecerán bloqueadas si no hay evidencia suficiente. Progreso: 0%.
Worked for 4 mins 38 sec
Fase 10 no pudo ejecutarse porque no quedan ACUs disponibles. No se modificó el proyecto.
Completado:
- Se reconciliaron ambos adjuntos; son idénticos.
- Se definió el alcance exacto de los 21 MPN faltantes y sus criterios de aprobación.
Pendiente:
- Investigación oficial y clasificación individual.
- Aplicación exclusiva de metadatos aprobados.
- Revisión Manufacturer Part Number antes/después.
- Reporte final Fase 10.
BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION.
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Phase 9 — Effective Capacitance and C15 Connection Review
State: BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION
Scope: Read-only qualification of C2, C13, C14 and C15. C12 was already closed at approximately 15.54 µF effective at 5 V versus the calculated LM5164 minimum of 3.1 µF. No schematic, PCB, BOM, placement, routing or component changes were made.
Scope: Read-only qualification of C2, C13, C14 and C15. C12 was already closed at approximately 15.54 µF effective at 5 V versus the calculated LM5164 minimum of 3.1 µF. No schematic, PCB, BOM, placement, routing or component changes were made.
Final dispositions
Table
| Category | Ref | Candidate | Official evidence and worst-case assessment | IC/rail requirement | Disposition |
|---|---|---|---|---|---|
| PENDING_APPROVAL | C2 | Fenghua 0603B475K100NT, LCSC C108342; 4.7 µF ±10%, 10 V, X7R, 0603 | Fenghua confirms ±10% initial tolerance and X7R temperature change of ±15% from −55°C to +125°C. The official series sheet and official product page provide no part-specific numerical DC-bias curve at 3.3 V and no guaranteed aging rate. Before DC bias and aging, the conservative tolerance/temperature floor is 4.7×0.90×0.85 = 3.60 µF. Because the missing bias/aging terms can only reduce this value, an effective minimum cannot be guaranteed. | Silicon Labs CP2102N typical power diagrams require 4.7 µF and 0.1 µF bypass capacitors for each power pin, placed close to the pins. The present C2 is on RX_3V3, shared by U2 VDD and VREGIN. | PENDING_APPROVAL. The proposed 4.7 µF part cannot be shown to retain the stated 4.7 µF requirement under operating bias. Select a larger part with an official numeric bias curve, or obtain manufacturer characterization for this exact part. |
| PENDING_APPROVAL | C13 | Murata GCM21BR70J106KE22L, LCSC C126230; 10 µF ±10%, 6.3 V, X7R, 0805 | Murata confirms 10 µF, ±10%, X7R ±15%, −55°C to +125°C and states that DC bias and aging must be considered. The exact official SimSurfing entry exists, with measurement at 25°C after 60 s bias, but its static official output does not expose numerical values at 2.5 V or 4.2 V. Before DC bias and aging, the tolerance/temperature floor is 10×0.90×0.85 = 7.65 µF. The part needs at least 61.4% retention after bias/aging to remain above 4.7 µF, but that retention is not guaranteed by the accessible official data. | TI TPS63030 recommends at least 4.7 µF input capacitance, ceramic, close to VIN and PGND. C13 is correctly connected from AIRTAG_CELL_POS to AIRTAG_PACK_NEG at U8 input. | PENDING_APPROVAL. Correct rail/function and promising nominal margin, but no official numeric worst-case effective C at the maximum 4.2 V cell bias was obtainable. |
| PENDING_APPROVAL | C14 | Murata GRM21BZ71A226ME15L, LCSC C907991; 22 µF ±20%, 10 V, X7R, 0805 | Murata provides the exact SimSurfing C–DC-bias interface, but the official static output does not expose a numerical value at 3.0 V. Before DC bias and aging, the tolerance/temperature floor is 22×0.80×0.85 = 14.96 µF. To remain at or above TI’s 10 µF recommended nominal output value, at least 66.8% of that pre-bias floor must remain after bias/aging; this is not guaranteed by the accessible official data. | TI TPS63030 recommends 10 µF nominal output capacitance, ceramic, close to VOUT and PGND; larger values are allowed. C14 is correctly connected from AIRTAG_3V0 to AIRTAG_PACK_NEG. | PENDING_APPROVAL. Correct rail/function and nominal value, but no official numerical worst-case effective C at 3.0 V was obtainable. |
| CONNECTION_REVIEW_REQUIRED | C15 | Same available candidate GRM21BZ71A226ME15L / C907991 was considered only as a 22 µF option | The current schematic connects C15 from RX_3V3 to DGND_SERVICE. It therefore bulk-decouples U9’s VDDS/VDDS2/VDDS3/VDDS_DCDC input rail. It does not connect to CC1354_VDDR. U9 pins VDDR and VDDR_RF are tied together on CC1354_VDDR, but that net has no capacitor or DCDC inductor connection. | TI CC1354P10 distinguishes VDDS input supply from VDDR internal-regulator/DC-DC output. TI requires the 22 µF DCDC capacitor to remain on the VDDR net, including when the DC/DC converter is not used. TI separately calls for a 22 µF VDDS input capacitor for small coin-cell sources with high end-of-life source resistance to meet supply slew rate. | C15_CONNECTION_REVIEW_REQUIRED / BLOCKS_PCBA. C15 may be valid as a VDDS input bulk capacitor, but it cannot simultaneously satisfy the mandatory VDDR capacitor. A later authorized schematic correction must define the CC1354 power mode, add/assign a 22 µF capacitor from CC1354_VDDR to ground, and retain or resize the VDDS bulk capacitor according to the source impedance. Do not simply move C15 without deciding whether VDDS also requires 22 µF. |
Category summary
APPROVED_FOR_SCHEMATIC
- C12 only, carried forward from the completed work: approximately 15.54 µF effective at 5 V, above the calculated 3.1 µF LM5164 minimum.
PENDING_APPROVAL
- C2 — missing official exact numerical DC-bias and aging data at 3.3 V.
- C13 — exact Murata curve exists but numeric 4.2 V output was not obtainable from the accessible official interface.
- C14 — exact Murata curve exists but numeric 3.0 V output was not obtainable from the accessible official interface.
REJECTED
- None of C2, C13 or C14 is rejected electrically from the available evidence; all remain conservatively pending.
CONNECTION_REVIEW_REQUIRED
- C15 — currently on VDDS/RX_3V3, while the required VDDR 22 µF path is absent. This blocks PCBA until the CC1354 supply topology is corrected and verified.
Official sources
- Silicon Labs, CP2102N Data Sheet, Typical Connection Diagrams, Figures 2.1–2.3.
- Texas Instruments, TPS63030/TPS63031, SLVS696D, Section 9.2.2.3 Capacitor Selection.
- Texas Instruments, CC1354P10, SWRS267B, supply-pin descriptions, recommended operating-condition note for VDDS slew rate, and unused DC/DC guidance retaining the 22 µF capacitor on VDDR.
- Fenghua Advanced, official general MLCC series specification and official product listing for
0603B475K100NT. - Murata official reference sheet and SimSurfing entry for
GCM21BR70J106KE22. - Murata official SimSurfing entry and measurement conditions for
GRM21BZ71A226ME15.
No values were inferred from non-official MLCC curves. Where official numerical curve output was inaccessible, the result remains PENDING_APPROVAL rather than inventing effective capacitance.
Final dispositions
Category summary
APPROVED_FOR_SCHEMATIC
PENDING_APPROVAL
REJECTED
CONNECTION_REVIEW_REQUIRED
Official sources
