Placement and board sizing are complete, but routing was rolled back because the generated copper overlapped, and the requested four-layer stackup did not persist. I’m independently verifying the saved state and will attempt one focused stackup correction before finalizing.
State: BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION Scope: Read-only review of U9 (CC1354P106T0RGZR) power topology. No schematic, PCB, BOM, placement, routing or library changes were made.
1. Current power mode
The current schematic is not wired for active internal DC/DC operation and is not externally powering VDDR:
U9 pin 33 DCDC_SW has no inductor or net connection.
U9 pin 34 VDDS_DCDC is tied to RX_3V3, together with VDDS, VDDS2 and VDDS3.
U9 pins 45 VDDR and 48 VDDR_RF are joined on CC1354_VDDR.
CC1354_VDDR has no capacitor and no inductor connection.
C15 is 22 µF from RX_3V3 to DGND_SERVICE and therefore acts as VDDS input bulk capacitance.
This matches TI’s internal-LDO / DC/DC-disabled topology intent, but it is incomplete because the mandatory VDDR capacitor is absent. It is not an external-LDO supply of VDDR: TI states VDDR must be powered by the device’s internal DC/DC converter or internal LDO and must not supply external circuitry.
VDDR pin 45 and VDDR_RF pin 48 must remain directly connected together on CC1354_VDDR.
TI explicitly states that even when the DC/DC converter is not used, the inductor between DCDC_SW and VDDR may be removed, but VDDR and VDDR_RF must remain connected and the 22 µF DCDC capacitor must remain on the VDDR net.
Rating, dielectric and ESR
The CC1354P10 datasheet specifies the 22 µF value and VDDR-net placement, but does not specify a numerical ESR range, dielectric, or minimum capacitor voltage rating in the retrieved requirement. The internally regulated VDDR level is trimmed to approximately 1.68 V; boost mode is referenced at 1.95 V.
A practical candidate already under sourcing review is:
Murata GRM21BZ71A226ME15L
LCSC C907991
22 µF ±20%, 10 V, X7R, 0805
This candidate has ample voltage rating and appropriate ceramic construction, but remains PENDING_USER_APPROVAL because its official numerical DC-bias/aging effective capacitance has not been closed. TI’s requirement should not be converted into an invented ESR limit.
Placement
Place the capacitor immediately adjacent to U9’s VDDR/VDDR_RF pins and exposed-pad ground with the shortest possible loop. TI Section 10.1, page 73, requires the reference designs to be followed closely and calls special attention to DC/DC components, decoupling capacitors and ground connections.
3. C15 function
C15 currently connects RX_3V3 to DGND_SERVICE, so it is a VDDS input bulk capacitor, not the VDDR capacitor.
C15 should not be moved by assumption. TI separately requires a 22 µF VDDS input capacitor when a small coin-cell source has high worst-case end-of-life source resistance, to meet the falling-supply slew-rate requirement (Section 8.3, page 14). The present system’s source impedance and final battery are not fixed, so removing C15 is not justified.
Therefore the safe correction is to retain C15 provisionally on VDDS and add a separate dedicated VDDR capacitor.
4. Proposed pin-to-net topology
Internal-LDO / DC/DC-disabled topology matching the current intent
Table
U9 pin
Official function
Proposed net / connection
13
VDDS2
RX_3V3
22
VDDS3
RX_3V3
34
VDDS_DCDC
RX_3V3
44
VDDS
RX_3V3
33
DCDC_SW
Explicit NC; no inductor when DC/DC is disabled
45
VDDR
CC1354_VDDR
48
VDDR_RF
CC1354_VDDR
New C20 pin 1
22 µF VDDR capacitor
CC1354_VDDR
New C20 pin 2
Capacitor return
DGND_SERVICE
23
DCOUPL
CC1354_DCOUPL, with existing C18 to DGND_SERVICE; C18 value must be independently checked against the exact TI reference design before fabrication
49 / EGP
Exposed ground pad
DGND_SERVICE, low-impedance ground connection
C15 pin 1
VDDS bulk
RX_3V3
C15 pin 2
VDDS bulk return
DGND_SERVICE
Designator C20 is proposed to avoid repurposing C15 and to make the two distinct 22 µF functions explicit. No component has been created.
Decision classification
APPROVED_TO_IMPLEMENT
Keep U9 pins VDDS, VDDS2, VDDS3 and VDDS_DCDC on RX_3V3.
Keep VDDR and VDDR_RF joined on CC1354_VDDR.
Keep DCDC_SW unconnected if the project formally selects internal-LDO mode.
Add one dedicated 22 µF capacitor from CC1354_VDDR to DGND_SERVICE close to U9.
Keep C15 on RX_3V3 pending final source-impedance review.
These topology statements follow TI Table 7-1 and Table 7-2.
PENDING_USER_APPROVAL
Formal selection of internal-LDO / DC/DC-disabled mode rather than adding the DC/DC inductor and using converter mode.
Use designator C20 for the new VDDR capacitor.
Use Murata GRM21BZ71A226ME15L / C907991 as the 22 µF VDDR candidate, subject to effective-capacitance closure.
BLOCKED_BY_MISSING_INFORMATION
Final battery/source type and worst-case end-of-life source impedance; this decides whether TI’s conditional 22 µF VDDS input requirement makes C15 mandatory.
Official numerical DC-bias/aging data confirming the selected VDDR capacitor retains suitable effective capacitance.
Exact reference-design confirmation of DCOUPL capacitor value and physical implementation before fabrication.
Any decision to enable the internal DC/DC converter; that would require an official-reference-design inductor and layout and is outside this review.
Official TI references
Section 7.2, Table 7-1, pages 8–9: pin functions for DCDC_SW, DCOUPL, VDDR, VDDR_RF, VDDS, VDDS2, VDDS3 and VDDS_DCDC; EGP is the device’s only ground connection.
Section 7.3, Table 7-2 note (2), page 9: DC/DC-disabled connection and mandatory 22 µF capacitor on VDDR.