BQ25185 Charger Topology

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Phase 8 — Power Passives Qualification for JLCPCB

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State: BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION Scope: Sourcing and qualification only. No schematic, PCB, BOM, placement, ro...

flux

Phase 8 completed without schematic, PCB, BOM, placement, or routing changes.
  • C5 approved for schematic: Murata GRM21BR61E106KA73L, LCSC C84416.
  • R9 and remaining capacitors have exact candidates but remain pending pulse-energy or DC-bias validation.
  • The exact C14/C15 option is out of stock; an available 10 V X7R candidate is documented.
Phase 8 — Power Passives Qualification for JLCPCB
BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION.

flux

I’ll read the attachment and follow only its authorized scope for the current BENCH_ONLY project.

flux

Fase 9 quedó parcialmente investigada antes de agotarse los ACUs.
Completado:
  • Extraje requisitos oficiales para C2, C4/C6, C8/C9, C12 y C13/C14.
  • Confirmé que C12 ofrece aproximadamente 15.54 µF efectivos a 5 V, suficiente frente al mínimo calculado LM5164 de 3.1 µF.
  • Identifiqué que C15 está conectado a RX_3V3, pero el requisito TI de 22 µF corresponde a VDDR, por lo que su función debe revisarse.
Pendiente:
  • Obtener curvas oficiales numéricas de DC-bias para C2, C13 y C14/C15.
  • Emitir los veredictos finales por designador.
  • Crear el reporte Fase 9 y actualizar las notas de sourcing.
No se modificaron esquema, PCB, BOM, placement ni routing. BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION.
Resume Fase 9
Create report
Review C15 connection
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J1 Library Gap and Footprint Validation Plan
State: BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION
Visible progress: Documentation correction 100% | Exact Flux entry 0% | PCB release 0%
Approved identity
  • Manufacturer: JAE
  • MPN: DX07S016JA3R1500
  • LCSC/JLCPCB: C3197625
  • Exact Flux entry: not found
  • Current JA1 entry: UNSAFE_PROXY / BLOCKS_PCB
  • Gap state: J1_LIBRARY_GAP / CUSTOM_OR_IMPORTED_FOOTPRINT_REQUIRED
Document authority
  • Use JAE SJ122205 for connector mechanics and the PCB land pattern.
  • Do not use JAE SJ122206 for pads, shell tabs, holes/slots, cutout, datum, orientation, or PCB dimensions; it is packaging/reel documentation.
Required validation checklist
The exact custom/imported entry must be checked against SJ122205 for:
  1. Every electrical pad and its dimensions/coordinates.
  2. Pin numbering and USB-C orientation.
  3. Shell-tab dimensions and locations.
  4. Plated/non-plated holes and slots.
  5. Required board cutout or edge relief.
  6. Board-edge datum and connector setback.
  7. Top/bottom and mating orientation.
  8. Permitted PCB thickness and shell-DIP engagement.
  9. Overall connector envelope and enclosure interference.
Independent 1:1 comparison
After authoring/importing, compare the complete footprint 1:1 against the exact EasyEDA library footprint for C3197625. Any discrepancy must be resolved against JAE SJ122205; EasyEDA is a cross-check, not the governing source.
Stop gate
Do not replace J1, modify its PCB footprint, or substitute JA1/another USB-C connector until the checklist is complete. The project remains BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION.

  • Approved identity

  • Document authority

  • Required validation checklist

  • Independent 1:1 comparison

  • Stop gate