U2 to U4 Connection Plan

Task unable to complete.

1:21

Accessing knowledge.
Read schematic for U2, J10.
Read layout for U2, J10.
Editing layout rules.
Read layout.

Updated 72 layout rules

0:01

Set PB20/A0_6's layer to "Top"

Set PB20/A0_6's connectedLayers to "Top"

Set PB20/A0_6's size to "10mil"

Set PB20/A0_6's minKeepOut to "net(20mil) polygon(20mil)"

Set PB20/A0_6's autoLayoutPriority to "1"

Set PB20/A0_6's preferredTraceWidths to "10mil"

Set PA24/A0_3's layer to "Top"

Set PA24/A0_3's connectedLayers to "Top"

Set PA24/A0_3's size to "10mil"

Set PA24/A0_3's minKeepOut to "net(20mil) polygon(20mil)"

Set PA24/A0_3's autoLayoutPriority to "1"

Set PA24/A0_3's preferredTraceWidths to "10mil"

Set PB18/A1_5's layer to "Top"

Set PB18/A1_5's connectedLayers to "Top"

Set PB18/A1_5's size to "10mil"

Set PB18/A1_5's minKeepOut to "net(20mil) polygon(20mil)"

Set PB18/A1_5's autoLayoutPriority to "1"

Set PB18/A1_5's preferredTraceWidths to "10mil"

Set PA26/A0_1 INT TO HOST's layer to "Top"

Set PA26/A0_1 INT TO HOST's connectedLayers to "Top"

Set PA26/A0_1 INT TO HOST's size to "10mil"

Set PA26/A0_1 INT TO HOST's minKeepOut to "net(20mil) polygon(20mil)"

Set PA26/A0_1 INT TO HOST's autoLayoutPriority to "1"

Set PA26/A0_1 INT TO HOST's preferredTraceWidths to "10mil"

Set VDD's layer to "Top"

Set VDD's connectedLayers to "Top"

Set VDD's size to "10mil"

Set VDD's minKeepOut to "net(20mil) polygon(20mil)"

Set VDD's autoLayoutPriority to "1"

Set VDD's preferredTraceWidths to "10mil"

Set PA21/A1_7/VREF-'s layer to "Top"

Set PA21/A1_7/VREF-'s connectedLayers to "Top"

Set PA21/A1_7/VREF-'s size to "10mil"

Set PA21/A1_7/VREF-'s minKeepOut to "net(20mil) polygon(20mil)"

Set PA21/A1_7/VREF-'s autoLayoutPriority to "1"

Set PA21/A1_7/VREF-'s preferredTraceWidths to "10mil"

Set PA23 VREF+'s layer to "Top"

Set PA23 VREF+'s connectedLayers to "Top"

Set PA23 VREF+'s size to "10mil"

Set PA23 VREF+'s minKeepOut to "net(20mil) polygon(20mil)"

Set PA23 VREF+'s autoLayoutPriority to "1"

Set PA23 VREF+'s preferredTraceWidths to "10mil"

Set PB24/A0_5's layer to "Top"

Set PB24/A0_5's connectedLayers to "Top"

Set PB24/A0_5's size to "10mil"

Set PB24/A0_5's minKeepOut to "net(20mil) polygon(20mil)"

Set PB24/A0_5's autoLayoutPriority to "1"

Set PB24/A0_5's preferredTraceWidths to "10mil"

Set PA25 GUARDBAND's layer to "Top"

Set PA25 GUARDBAND's connectedLayers to "Top"

Set PA25 GUARDBAND's size to "10mil"

Set PA25 GUARDBAND's minKeepOut to "net(20mil) polygon(20mil)"

Set PA25 GUARDBAND's autoLayoutPriority to "1"

Set PA25 GUARDBAND's preferredTraceWidths to "10mil"

Set Net 49's layer to "Top"

Set Net 49's connectedLayers to "Top"

Set Net 49's size to "10mil"

Set Net 49's minKeepOut to "net(20mil) polygon(20mil)"

Set Net 49's autoLayoutPriority to "1"

Set Net 49's preferredTraceWidths to "10mil"

Set PA22/A0_7's layer to "Top"

Set PA22/A0_7's connectedLayers to "Top"

Set PA22/A0_7's size to "10mil"

Set PA22/A0_7's minKeepOut to "net(20mil) polygon(20mil)"

Set PA22/A0_7's autoLayoutPriority to "1"

Set PA22/A0_7's preferredTraceWidths to "10mil"

Set PA27/A0_0 I2C or UART/SPI's layer to "Top"

Set PA27/A0_0 I2C or UART/SPI's connectedLayers to "Top"

Set PA27/A0_0 I2C or UART/SPI's size to "10mil"

Set PA27/A0_0 I2C or UART/SPI's minKeepOut to "net(20mil) polygon(20mil)"

Set PA27/A0_0 I2C or UART/SPI's autoLayoutPriority to "1"

Set PA27/A0_0 I2C or UART/SPI's preferredTraceWidths to "10mil"

flux

Work done
  • Identified the U2↔J10 nets: PB18/A1_5, Net 49, PA21/A1_7/VREF-, PA22/A0_7, PB20/A0_6, PB24/A0_5, PA23 VREF+, PA24/A0_3, PA25 GUARDBAND, PA26/A0_1 INT TO HOST, PA27/A0_0 I2C or UART/SPI, and VDD.
  • Applied Top Layer-only, 10 mil trace width, 20 mil clearance, and highest routing priority constraints to those nets.
  • Verified the stackup is 6-layer with Top as a signal layer, and the existing trace rule remains 10 mil with clearance rules at about 20 mil.
Success criteria review
  • ✅ U2↔J10 nets identified and constrained to Top Layer.
  • ✅ 10 mil trace width and 20 mil clearance were preserved/applied for those nets.
  • ❌ Actual copper routing and clean DRC/airwire closure could not be completed here; the current DRC still reports airwires in the design, including U2↔J10-related airwires.
Next steps
Run the PCB editor routing pass for the constrained U2↔J10 nets, then re-check DRC/airwires. Routing guidance requires resolving airwires, then re-validating DRC after the routing pass .
Show remaining airwires
Check routing blockers
Export DRC report
List layer violations
Sign up to send
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IPP018C_Schematic-1 wpTi thumbnail
Imported from Altium.

Properties

Properties describe core aspects of the project.

Pricing & Availability

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Controls