Finding Milk-V Duo S Part

flux

Work done
  • Removed P3 and replaced it with two new 1 x 26, 1.27 mm header placeholders: J13 and J14
  • Placed J13 and J14 parallel in the layout with 22.86 mm center-to-center spacing
  • Re-mapped required signals onto the new headers:
    • 5V_MAIN -> J13 pin 1
    • GND -> J13 pin 3
    • J1 pin 3 / USB_SRC_DP -> J13 pin 10
    • J1 pin 11 / USB_SRC_DM -> J13 pin 11
    • J3 to J10 PWM signals -> J14 pins 1 through 8
    • MAVLink RX from J12 pin 4 -> J14 pin 16
  • Renamed the project to reflect the updated module placeholder target
Success criteria review
  • ✅ The original P3 placeholder was removed
  • ✅ Two new 26-pin headers were added and placed with 22.86 mm spacing
  • ✅ 5V_MAIN, GND, USB D+ and D-, and J3 through J10 mappings were connected to the new headers
  • ✅ The schematic and layout now reflect the new Milk-V Duo S header placeholder approach
  • ⚠️ The plan requested MAVLINK_FC on header 2 pins 15 and 16, but the project currently exposes only MAVLINK_FC_RX on J12 pin 4. I mapped that existing signal to J14 pin 16. There was no matching TX net present to place on pin 15 without inventing a new connection.
Next steps
  • The new header footprints are placed, but the PCB still has unrouted airwires for these newly connected nets. If you want, I can continue by preparing the remaining signal plan around J13 and J14 for manual routing.
S

semenetsvladyslav

can you route all my wires?

flux

Not directly from this chat session.
I can help prepare routing by inspecting the layout, checking airwires/DRC, and setting layout rules, but I don’t currently have a direct routing control tool exposed here to finish “route all wires” for you. The available guidance for project modification shows routing as part of the PCB layout workflow, with inspect -> setup -> annotate -> group -> ui-place -> route, and emphasizes using layout-oriented tools for that workflow
What I can do next:
  • inspect the current PCB and tell you what remains unrouted
  • set or tighten layout rules before routing
  • review DRC/airwires after you run Auto-Layout / Auto-Route
  • help optimize placement around J13 and J14 to make routing easier
If you want, I can do the most useful next step now: audit the remaining unrouted nets and placement issues.
Audit unrouted nets
Check DRC airwires
Tighten layout rules
Placement around J2
Sign up to send

Files

Schematic

Layout

Preview

Design Notes
Power Architecture
Diagram



  
    
  
  
    
  
















DC Input node_7V to node_16V
Input Connector
TVS Protection
Input Bulk And HF Decoupling
Primary Buck node_5V node_5A
5V Rail
Secondary Buck 3.3V node_3A
3.3V Modem Rail
Chosen Defaults
  • Input connector: screw terminal, chosen for carrier-board flexibility and easier field wiring.
  • Primary architecture: dedicated high-current 5V buck from VIN.
  • Secondary architecture: dedicated 3.3V buck derived from 5V rail to reduce dissipation versus an LDO at 3A.
  • Protection: TVS diode directly across input and ceramic plus bulk input capacitors.
  • Regulator support parts follow the selected regulator datasheet recommendations.
Implemented Schematic
  • Input connector uses a 2-pin 5.08 mm screw terminal.
  • Input protection uses an SMBJ18A TVS across the protected VIN input.
  • Input decoupling includes 100uF bulk plus 22uF ceramic at VIN.
  • Primary regulator uses TPS56528 with 4.7uH inductor, 54.9k / 10k feedback divider, bootstrap capacitor, and dual 22uF bulk output capacitors on 5V.
  • Secondary regulator uses TPS62132 fixed 3.3V with 2.2uH inductor, 22uF input, 22uF output, 100nF AVIN bypass, 3.3nF soft-start capacitor, and dedicated 3.3V modem rail.
Verification
  • ERC checks for floating pins, missing power, single-pin nets, and undriven nets all passed.
  • Named rails include VIN_PROTECTED, 5V_MAIN, and 3V3_MODEM.
Schematic Cleanup And Initial Layout Plan
  • Intentional unused pins on P3, J1, and J11 are now documented as no-connects for this revision to reduce review ambiguity until exact production-specific interfaces are finalized.
  • P3 remains a placeholder castellated interface and is excluded from BOM and pick-and-place.
  • The layout is now constrained to a 100 mm x 100 mm board with a 4-layer stackup.
  • Layer 2 is reserved as the primary ground reference plane and Layer 3 is assigned as a power plane.
  • Board-level routing baseline now uses 1.0 mm minimum and preferred trace width to support high-current 5V_MAIN and GND routing, with pours expected for the main distribution path.
  • Floorplan intent for the next layout pass:
    • P3 centered on the top side.
    • J1 moved to the bottom side in a sandwich arrangement below P3.
    • J11 placed immediately adjacent to P3 to keep camera routing short.
    • J3 through J10 aligned along one board edge.
    • U1, U2, IC1, and the main power-entry region kept away from camera routing.
    • TP1 and TP2 placed very close to the Duo S USB breakout area on P3.
  • Layout rule preparation for manual routing:
    • HIGH_POWER equivalent applied to 5V_MAIN and GND with 1.0 mm trace width, protected routing, and highest routing priority.
    • MIPI_CSI equivalent applied to all J11 camera nets with 0.15 mm protected high-priority routing.
    • USB_SRC_DP and USB_SRC_DM are marked as protected high-priority nets for short paired manual routing.
    • Formal matched-length and impedance constraints are still pending because the current rule editor did not expose those controls in this run.
Carrier Board Expansion
  • Added TP1 and TP2 as manual USB bridge source pads labeled USB_SRC_DP and USB_SRC_DM.
  • Connected TP1 to J1 pin 3 and TP2 to J1 pin 11 for the modem USB pair.
  • Added J11 as a Raspberry Pi style 15-pin 1.0 mm CSI FPC connector using SFW15R-2STE1LF.
  • Added J3 through J10 as eight 3-pin servo headers with shared GND and 5V_MAIN rails.
  • Added J12 as a 4-pin MAVLINK_FC UART header with pin order GND, 5V_MAIN, TX, RX.
  • CSI connector mapping follows the Duo S Raspberry Pi camera interface ordering: 3V3, SDA, SCL, sensor clock, sensor reset, clock lane pair, data lane 1 pair, data lane 0 pair, and grounds.
  • USB routing requirement for this revision is a short paired connection only; no formal impedance rule is applied.
Milk-V Duo S Connector Integration
  • Added P3 as a standard 2x20 2.54 mm header for the Milk-V Duo S module.
  • Connected pin 39 and pin 40 to 5V_MAIN.
  • Connected pins 3, 18, 33, 34, and 38 to GND.
  • Labeled UART0 on pins 16 and 17 as DEBUG_UART_TX and DEBUG_UART_RX.
  • Labeled UART1 on pins 1 and 2 as MAVLINK_UART_TX and MAVLINK_UART_RX.
M.2 Modem Integration
  • Added J1 as an M.2 Key B modem socket for a 3042 cellular modem module.
  • Connected available J1 3.3V power pins 2, 4, 70, 72, and 74 to the 3V3_MODEM rail.
  • Connected modem USB lines as USB_SRC_DP on J1 pin 3 and USB_SRC_DM on J1 pin 11 through dedicated manual bridge pads TP1 and TP2.
  • Added J2 as a Micro-SIM socket and wired SIM_VCC, SIM_RST, SIM_CLK, and SIM_IO to J1 pins 36, 30, 32, and 34 respectively.
  • Tied J1 shield pins and J2 shield/card ground pins to GND.
  • Added FULL_CARD_POWER_OFF between J1 pin 6 and P3 pin 4 as the selected Milk-V Duo S GPIO placeholder.
  • Pending confirmation: exact Milk-V Duo S CSI and UART placeholder-to-real-pad correlation if the Duo S placeholder part is later replaced with an exact module interface.

  • Power Architecture

  • Chosen Defaults

  • Implemented Schematic

  • Verification

  • Schematic Cleanup And Initial Layout Plan

  • Carrier Board Expansion

  • Milk-V Duo S Connector Integration

  • M.2 Modem Integration