# Seeed Studio XIAO ESP32S3 (Component) ## Description Production-Ready PCB Design Verification ## Component Details - **Owner:** seeedstudio - **Created:** 11/7/2023 - **Last Updated:** 2/5/2024 - **Visibility:** Public - **DRC Reviews: design_rule_check_airwires:** Clean - **Hole3_inset:** 0mm - **Manufacturer Part Number:** 113991114 - **Hole4_inset:** 0mm - **DRC Reviews: design_rule_check_missing_footprints:** Clean - **Domain:** Consumer Electronics - **DRC Issues:** [] - **Max Y:** 352.7mm - **Datasheet URL:** https://files.seeedstudio.com/wiki/SeeedStudio-XIAO-ESP32S3/res/esp32-s3_datasheet.pdf - **DRC Violations:** [] - **Review Summary:** All requested ERC and DRC reviews are clean. Manufacturing review: Clean. - **Hole1_inset:** 0mm - **BoardExtent_MinX:** 362.6mm - **Hole3_pad_coords:** (367.6, -150) - **Hole4_pad_coords:** (367.6, -210) - **System Architecture:** graph LR XIAO[XIAO ESP32S3] PSU[Power Subsystem] NEXTION[Nextion Connector] UART[UART Link] KEEP[Keepout Domain] TEST[Test Pad Domain] PSU -->|5V/GND| XIAO XIAO -->|TX/RX| NEXTION KEEP -.-> XIAO TEST --> XIAO TEST --> NEXTION - **Purchase Url:** https://www.seeedstudio.com/XIAO-ESP32S3-p-5627.html - **BoardExtent_MinY:** -215mm - **Min X:** -477.1mm - **ERC Issues:** [] - **Manufacturing Issues:** Missing footprints: C1, C2, C4, C5, R1, R2, J2, J3, Hole1, Hole2, Hole3, Hole4. No deprecated rules detected. - **Design Rule Check Status:** Clean - **Max X:** 367.6mm - **Missing MPNs:** C1, C2, C4, C5, R1, R2, J2, J3, Hole1, Hole2, Hole3, Hole4 - **Manufacturing Review Status:** Clean - no errors from design_rule_check_manufacture_part_number, resistor_power_rating, capacitor_voltage_rating - **BoardExtent_MaxY:** -25mm - **ERC Reviews: decoupling_caps:** Clean - **Hole1_pad_coords:** (367.6, -30) - **Product Info Url:** https://wiki.seeedstudio.com/xiao_esp32s3_getting_started/ - **Footprint:** XIAO Footprint Designator - **BoardExtent_MaxX:** 372.6mm - **Hole2_pad_coords:** (367.6, -90) - **ERC Reviews: pull_up_pull_down:** Clean - **XIAO Height:** 17.5mm - **XIAO Width:** 23.5mm - **Manufacturer Name:** Seeed Studio - **Hole2_inset:** 0mm - **Antenna Keepout Region:** Polygon coordinates: (x1, y1), (x2, y2), (x3, y3), (x4, y4) — covering the ESP32S3 onboard module’s antenna edge. Referenced from the top right of the XIAO footprint: Width 7.0 mm, Height 5.5 mm. Affected layers: Top, Bottom, TopCopper, BottomCopper, TopSilkscreen, BottomSilkscreen, TopMask, BottomMask. Clearance: no copper/fills/traces/components allowed; keepout is for all layers. Final coordinates and reference to be documented per final XIAO footprint placement in layout documentation. - **Part Type:** Microcontroller - **Min Y:** -490.2mm - **System Architecture:** graph LR XIAO[XIAO ESP32S3] PSU[Power Subsystem] NEXTION[Nextion Connector] TEST[Programming/Test Pads] MOUNT[Mounting Holes] ANTENNA[Antenna Keepout] PSU -->|5V/GND| XIAO PSU -->|5V/GND| NEXTION XIAO -->|UART TX→RX| NEXTION XIAO -->|UART RX←TX| NEXTION TEST --> XIAO TEST --> NEXTION MOUNT -.-> XIAO ANTENNA -.-> XIAO - **Used in:** 670 projects - **Stars:** 15 - **Forks:** 20 ## Distributor Pricing (qty 1) *Pricing shown for quantity 1. For price breaks and other quantities, open in Flux.* | Distributor | Unit Price (qty 1) | Stock | |------------|--------------------|-------| | [Arrow](https://www.arrow.com/en/products/113991114/seeed-technology-limited.html?utm_currency=USD&region=nac) | $6.914 | 16 | | [Digi-Key](https://www.digikey.com/en/products/detail/seeed-technology-co-ltd/113991114/19285530) | $7.49 | 393 | | [LCSC](https://www.lcsc.com/product-detail/C20467913.html) | $11.8429 | 0 | | [Mouser](https://www.mouser.com/ProductDetail/Seeed-Studio/113991114?qs=3Rah4i%252BhyCEHk7Z4Wa73Xg%3D%3D) | $7.49 | 571 | | [Verical](https://www.verical.com/pd/seeed-development-limited--embedded-system-development-tools-113991114-12155381?utm_currency=USD) | $6.914 | 16 | - **Part Type:** Integrated Circuits - **Sub-Type:** Logic - **Manufacturer:** Seeed - **MPN:** 113991114 - **Mount Type:** Stud - **Pin Count:** 14 - **Logic Function:** AND ## Pins | Pin | Name | Type | |-----|------|------| | 1 | TOUCH1_GPIO1_A0_D0 | | | 2 | TOUCH2_GPIO2_A1_D1 | | | 3 | TOUCH3_GPIO3_A2_D2 | | | 4 | TOUCH4_GPIO4_A3_D3 | | | 5 | TOUCH5_GPIO5_SDA_A4_D4 | | | 6 | TOUCH6_GPIO6_SCL_A5_D5 | | | 7 | TX | | | 8 | TP2 - J2 Pin_3 | | | 9 | D8_A8_SCK_GPIO7_TOUCH7 | | | 10 | D9_A9_MISO_GPIO8_TOUCH8 | | | 11 | D10_A10_MOSI_GPIO9_TOUCH9 | | | 12 | 3V3 | | | 13 | GND | | | 14 | 5V | | --- *Generated from [https://www.flux.ai/seeedstudio/seeed-studio-xiao-esp32s3~jt](https://www.flux.ai/seeedstudio/seeed-studio-xiao-esp32s3~jt)*