• PowerBoard

    PowerBoard

    Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules

    spurgazr

    a month ago

    47 Comments


  • IEEE Workshop Astable Multivibrator

    IEEE Workshop Astable Multivibrator

    Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules

    samlobert

    4 months ago

    2 Uses

    17 Comments


  • Relay Driver TPL9201 SSR EM JLCPCB SIGDOWN

    Relay Driver TPL9201 SSR EM JLCPCB SIGDOWN

    Use this template if you're planning to get your multi layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules

    darderik

    3 months ago

    2 Uses

    3 Comments


  • [4-layer] OSHPARK Constraints

    [4-layer] OSHPARK Constraints

    Use this template if you're planning to get your board manufactured in OSHPARK. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules OSHpark 4-layer stackup specs: Top overlay or silkscreen: 1 mil thick Top solder mask or solder resist: 1 mil thick Top copper: 1.7 mil thick on 1 oz copper Dielectric: 7.96 mil thick FR408HG 2113 Mid layer 1: 0.68 mil thick on 0.5 oz copper Dielectric core: 39 mil thick FR408HR Mid layer 2: 0.68 mil thick on 0.5 oz copper Dielectric: 7.96 mil thick FR408HG 2113 Bottom copper: 1.7 mil thick on 1 oz copper Bottom solder mask or solder resist: 1 mil thick
Bottom overlay or silkscreen: 1 mil thick

    chrisberry

    &

    elizabetgoldcorde736380
    tarra-tomato-wilhuff-tarkin171165
    zealatflux
    +2

    a year ago

    1 Comment


  • [2-layer] JLCPCB Constraints 9v9m

    [2-layer] JLCPCB Constraints 9v9m

    Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules

    spurgazr

    2 months ago


  • test missing ground connection submodule Relay Driver TPL9201 SSR EM JLCPCB SIGUP

    test missing ground connection submodule Relay Driver TPL9201 SSR EM JLCPCB SIGUP

    Use this template if you're planning to get your multi layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules

    greg

    2 months ago


  • [2-layer] OSHPARK Constraints

    [2-layer] OSHPARK Constraints

    Use this template if you're planning to get your board manufactured in OSHPARK. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules

    kennyt

    10 months ago


  • Relay Driver TPL9201 SSR EM JLCPCB SIGUP

    Relay Driver TPL9201 SSR EM JLCPCB SIGUP

    Use this template if you're planning to get your multi layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules

    darderik

    2 months ago

    212 Uses