Custom-outline PCB with eight edge-distributed phototransistor channels, shared VIN and GND, and eight separate analog outputs.

Competition PCB for a to and fro memory robot using through-hole components only. Target layout is maximum 120 mm x 70 mm, 2-layer maximum with top-layer routing only, 0.5 mm trace width minimum design intent, 0.3 mm clearance minimum, restricted solder mask outside the board center, and manufacturing freeze before 15 April 2026. Planned architecture uses a simple 5 V control and drive system with sensor inputs, memory/control logic, motor-driver stage, user controls, and edge-access debug/test points.