Heimdall Bypass Schematic

Thought for 44 mins 14 sec
Reading "power-budget-and-height-review" project doc.
Getting a schematic overview.
Checking 8 design areas.
Thought for 7 sec — Planning layout adjustments
4/6 Regroup the complete power section adjacent to J1 and recheck placement

Replace J1 with Molex 43650-0200 and rewire it

Replace polymer input bank with four 10uF 50V X7R 1210 capacitors and add RC damping

Verify revised power input schematic and ERC

Regroup the complete power section adjacent to J1 and recheck placement

Resume routing, pours, stitching, and silkscreen cleanup

Run final DRC and report board dimensions and tallest component

Accessed knowledge for the next task.
Thought for 22 sec
Steering PCB Placement Setup…
Thought for 14 sec
Awaiting 1 background task
Thought for 11 sec
Awaiting 1 background task
Thought for 10 sec
Checking PCB Placement Setup progress…
Thought for 9 sec
Awaiting 1 background task
Received notification from "PCB Placement Setup" that it finished — picking the work back up.

flux

The corrected power section is now consolidated beside J1 on the unchanged 48 × 75 mm board, with all 89 components top-side and no reported placement violations. I’m running an independent routing preflight now, then I’ll resume the existing route job if the platform allows it.

flux

Implemented the requested corrections:
  • J1 replaced with Molex 43650-0200 THT Micro-Fit.
  • Added four CL32B106KBJNNNE input capacitors and the 10 µF + 1.5 Ω damping branch.
  • Regrouped the complete power section beside J1.
  • Board remains 48 × 75 mm, with 89 top-side components.
  • Tallest component is J1 at 5.57 mm.
  • Auto-routing completed partially, leaving 7 airwires.
Remaining
  • Four USB-C-to-ESD-array connections.
  • Two CP2102N ground-pad connections to the ground fill.
  • One USB_ENUM_OK connection between D14 and U3.
  • Copper pours/stitching, silkscreen cleanup, and final DRC.
Execution is paused because no ACUs remain.
Review remaining airwires
Check DRC/ERC issues
Optimize USB ESD placement
Manufacturing readiness checklist
Document power decisions
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Files

Schematic

Layout

Preview

Project Specification
Project Overview
  • Product: Heimdall Bypass
  • Status: Draft
  • Compact automotive Bluetooth accessory that presents as a headset to a motorcycle infotainment system.
Intended Use
  • Installed under a motorcycle seat in a 3D-printed enclosure.
  • Powered from switched 12 V automotive power or USB-C during programming/service.
  • Production-intent, single-sided SMT assembly on a compact four-layer PCB.
What the Device Should Do
  • Run Bluetooth firmware on an ESP32-WROOM-32E-N4.
  • Program and monitor the ESP32 through USB-C and CP2102N UART.
  • Automatically enter download mode using DTR/RTS transistor control.
  • Provide a user-accessible GPIO0 pair/factory-reset button and addressable status LED.
  • Survive reverse polarity, cranking dips, and automotive input transients within the qualified protection envelope.
Main Features
  • ESP32-WROOM-32E-N4, footprint-compatible with ESP32-WROOM-32UE.
  • Protected switched 12 V input.
  • USB-C USB 2.0 programming and alternate power.
  • Six test pads: 3V3, GND, EN, GPIO0, TXD0, RXD0.
  • Four 2.7 mm non-plated mounting holes.
System Architecture
Diagram



  
    
  
  
    
  





















Switched 12 V
Fuse + reverse polarity + TVS + bulk
Automotive buck node_3V3
USB-C 5 V
Isolated USB node_3V3 path
3V3 source ORing
ESP32-WROOM-32E
CP2102N USB-UART
WS2812B-Mini
GPIO0 button
Hardware Subsystems
Compute and Radio
  • U1 at a board edge with antenna facing outward, preferably overhanging.
  • Exact Espressif antenna keepout enforced on every copper and silkscreen layer.
  • GPIO6-GPIO11 unavailable because they connect to module flash.
Automotive Power
  • Input order: J1 → 1.1 A hold PPTC → 60 V P-channel reverse-polarity MOSFET → 33 V standoff unidirectional TVS → 100 µF/50 V bulk → buck regulator.
  • The final regulator and TVS clamp combination must retain guaranteed voltage margin during load dump; the provisional MPQ9841-AEC1 candidate requires validation because its 36 V maximum is close to a 33 V TVS clamp region.
  • 3.3 V rail must support at least 500 mA transient load and 1 A regulator capability.
USB-C and Programming
  • USB 2.0 Type-C receptacle with independent 5.1 kΩ Rd resistors on CC1 and CC2.
  • CP2102N-A02-GQFN28 powered from USB VBUS without back-feeding the automotive rail.
  • USB data nets connect to the bridge; UART0 connects TXD→GPIO3/RXD0 and RXD→GPIO1/TXD0.
  • DTR/RTS drive the standard two-NPN ESP32 automatic-reset circuit.
  • Add appropriate USB D+/D− ESD protection.
Boot, Control, and Indication
  • EN: 10 kΩ pull-up to 3V3 and 1 µF to GND.
  • GPIO0: 10 kΩ pull-up and momentary switch to GND.
  • WS2812B-Mini on a safe spare GPIO with 100 nF local decoupling.
Interfaces and Connections
  • J1: pin 1 +12V SW, pin 2 GND.
  • J2: USB-C power and USB 2.0 data.
  • Test pads: 3V3, GND, EN, GPIO0, TXD0, RXD0.
Power and Runtime Expectations
  • 12–14.4 V nominal motorcycle supply with cranking dips and transient exposure.
  • USB-C can operate/program the board independently.
  • No battery or charging subsystem.
Power Tree and Power Budget

Table

RailLoadTypical estimatePeak/design
3V3ESP32-WROOM-32E80–240 mA500 mA transient
3V3CP2102N-side interface contributionlow tens of mA<100 mA
3V3WS2812B-Ministatus-dependentup to ~60 mA full white
3V3Passives/leakagesmall<10 mA
3V3 total~150–300 mA~670 mA conservative
  • Select a ≥1 A 3.3 V source with transient and thermal margin.
  • At 9 V cranking input and 85% efficiency, 670 mA at 3.3 V reflects to about 0.29 A input; the specified 1.1 A PPTC has ample current capacity but its hot resistance/drop must be checked.
Manufacturing and Assembly Expectations
  • Four layers: L1 signal/components, L2 solid GND, L3 power, L4 signal.
  • 1.6 mm FR-4, 1 oz outer copper, ENIG, 6/6 mil minimum, 0.3 mm minimum drilled hole.
  • Components only on top side.
  • Target board 25 × 55 mm or smaller.
Firmware-Relevant Hardware Requirements
  • UART0 programming through CP2102N.
  • Automatic flashing using DTR/RTS.
  • GPIO0 button doubles as pair/factory reset after boot.
  • One spare non-strapping GPIO drives the RGB LED.
Physical Design Expectations
  • J1 and J2 on accessible board edges, preferably opposite ends.
  • Four 2.7 mm NPTH holes, nominally 3 mm inset, adjusted as needed to avoid the mandatory antenna keepout.
  • SW1 aligned for an enclosure plunger; D3 aligned for a light pipe.
  • All polarized devices visibly marked.
  • Silkscreen: HEIMDALL BYPASS — Nordic 3D and a version string.
Important Design Decisions
  • Use a P-channel MOSFET rather than a series diode for reverse polarity.
  • Use a four-layer board and preserve an unbroken L2 ground reference except at the antenna keepout.
  • Treat USB D+/D− as a short, coupled USB 2.0 pair even though the supplied brief says controlled impedance is not required.
  • Do not allow either power source to back-feed the other.
Assumptions
  • Ambient and component temperature qualification will be selected for under-seat automotive conditions.
  • USB operation only needs default USB current capability; firmware should avoid sustained maximum radio plus full-white LED load from a weak USB host.
  • Board version starts at REV A unless changed later.
Change Notes
  • Initial specification captured from the supplied design brief.

  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Compute and Radio

  • Automotive Power

  • USB-C and Programming

  • Boot, Control, and Indication

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Change Notes