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KYB1 — Power Budget, GPIO Map, and Blockers
Product: Black Magick Heavy Industries KYB1
Model: BLKMGK-KYB1-BASIC
Live architecture: 69 keys, XIAO ESP32-C5, RAK3112, addressable RGB, microSD, dual USB-C, and three SMA connectors.
Model: BLKMGK-KYB1-BASIC
Live architecture: 69 keys, XIAO ESP32-C5, RAK3112, addressable RGB, microSD, dual USB-C, and three SMA connectors.
Checklist item 2 — I/O expansion and GPIO map
Two library-available Microchip MCP23017T-E/SO expanders were added.
- U5, address 0x20: A2/A1/A0 = 0/0/0. GPA0..GPA7 = ROW0, ROW1, ROW2, ROW3, ROW4, ROW5, ROW6, ROW7_AUX. GPB0..GPB7 = COL0..COL7. The existing switch/diode matrix topology and named ROW/COL nets are retained.
- U6, address 0x21: A2/A1/A0 = 0/0/1. GPA0=SD_CS, GPA1=SD_DETECT, GPA2=RAK_RESET_N, GPA3=RAK_BOOT, GPA4=RAK_READY_IRQ, GPA5=RGB_PWR_EN, GPA6=USB_C_CUR_OUT1, GPA7=USB_C_CUR_OUT2. TUSB320 outputs are open-drain with 10 kΩ pull-ups to 3.3 V. Truth table: OUT1/OUT2 = H/H unattached/default standby, H/L attached default current, L/H 1.5 A, L/L 3 A. Remaining GPIO and both expanders' interrupt pins are intentionally unused/no-connect.
- Shared I2C: U1 D4/GPIO23 = SDA and U1 D5/GPIO24 = SCL, each pulled to 3.3 V with 4.7 kΩ. Both ICs have 100 nF bypass capacitors. RESET pins share a 10 kΩ pull-up.
Final XIAO ESP32-C5 map
Table
| XIAO pin | GPIO | Function |
|---|---|---|
| D2 | 25 | BACKLIGHT_PWM |
| D3 | 7 | RGB_DATA_3V3 |
| D4 | 23 | I2C_SDA |
| D5 | 24 | I2C_SCL |
| D6 | 11 | UART TX to RAK UART RX (RAK_UART_RX) |
| D7 | 12 | UART RX from RAK UART TX (RAK_UART_TX) |
| D8 | 8 | SD_SCK |
| D9 | 9 | SD_MISO |
| D10 | 10 | SD_MOSI |
D0/GPIO1, D1/GPIO0 and JTAG/back-pad GPIO are unused. USB, BOOT/GPIO28, EN, RF/antenna functions and unavailable/internal flash pins are not assigned. SD chip-select/card-detect and slow RAK/RGB controls are on U6.
Power budget
Table
| Rail/load | Peak |
|---|---|
| 69 × SK6805-EC15 at full white | 1,304.1 mA @ 5 V |
| RAK3112 Wi-Fi TX | 340 mA @ 3.3 V |
| RAK3112 LoRa +22 dBm TX | 140 mA @ 3.3 V |
| microSD allowance | 200 mA @ 3.3 V |
| Known external 3.3 V simultaneous peak | 540 mA |
The SK6805 theoretical figure uses the same schematic/design assumption as the former 44-LED calculation: 18.9 mA per LED at full white. Thus 69 × 18.9 mA = 1,304.1 mA. At 90% buck efficiency the 540 mA 3.3 V rail reflects about 396 mA to 5 V. Known theoretical 5 V peak excluding XIAO is therefore about 1.700 A (1.3041 A + 0.396 A). The protected path should be treated as a 2 A-class requirement, while firmware must enforce lower RGB limits by source mode: 250 mA for unknown/default USB, 700 mA for an advertised 1.5 A source, and 1,200 mA for an advertised 3 A source. These are RGB limits, not total-input guarantees; radio TX and sustained SD writes remain serialized outside 3 A mode.
3.3 V peripheral regulator
Added U7 AP63203WU-7, fixed 3.3 V/2 A synchronous buck. Datasheet application values are implemented: 3.9 µH L1 (Isat specified 3 A), 10 µF input, 2 × 22 µF output, and 100 nF BST-SW capacitor. Output net
3V3_PERIPH supplies both RAK3112 VDD pins and the microSD rail. This provides substantial current and transient margin over the 540 mA known peak and avoids LDO thermal loss.Source-mode safety policy
- XIAO USB only / unknown or USB-default source: RGB rail disabled at startup; radio concurrency prohibited; brightness/current limited; microSD writes and radio TX serialized. Firmware must assume no more than the enumerated/default USB budget.
- External source advertises 1.5 A: reduced RGB brightness; avoid simultaneous Wi-Fi peak + LoRa TX + sustained SD writes.
- External source advertises 3 A or an accepted >=2 A PD contract: full mode permitted, still with RGB firmware current limiting.
- Full mode is never enabled merely because VBUS is present.
Checklist item 3 — dedicated USB-C input (completed)
Implemented a 5 V Type-C current-advertisement architecture without USB PD negotiation:
- J5 USB4235-03-C_REVA power-only USB-C receptacle. CC1 and CC2 are independent; USB data/SBU pins are intentionally no-connect. All VBUS contacts form
USB_C_VBUS_RAW; shell and ground contacts go to GND. - U8 TUSB320LAIRWBR in UFP GPIO mode: PORT=GND, EN_N=GND, ADDR floating, CC1/CC2 connected directly to J5. VBUS_DET uses R10=900 kΩ from raw VBUS, VDD has C59=100 nF, and raw VBUS has C58=1 µF. OUT1/OUT2 report attached default/1.5 A/3 A modes to U6 GPA6/GPA7.
- D59 SMF5.0A clamps raw VBUS to GND. It is a 5 V standoff, 200 W unidirectional TVS.
- U9 TPS25940LRVCR provides integrated back-to-back-FET true reverse blocking, inrush control, and current limiting. R13=24.9 kΩ sets 3.25 A minimum / 3.53 A typical current limit; C61=1.5 nF programs dV/dt; C60=100 nF bypasses the input. Output
USB_C_5V_EFUSEDhas C62=22 µF bulk. - U10 TPS2121RUXR combines
USB_C_5V_EFUSEDon priority IN1 with isolatedXIAO_USB_VBUSon IN2. CP2=GND and PR1=IN1 select fixed IN1 priority whenever valid. The mux provides reverse-current/cross-conduction blocking so neither connector back-powers the other. R14=29.8 kΩ sets 3.0 A minimum / 3.5 A typical current limit; C63=1 µF provides soft start. Both OUT pins feed existingUSB_5V_PROTECTED. - Existing
USB_5V_PROTECTEDcontinues to feed U7 AP63203WU-7 (3.3 V peripheral buck) and U4 TPS22995 RGB load switch. R15=100 kΩ pullsRGB_PWR_ENlow, keeping RGB hardware-off while U6 is reset or unconfigured.
Operating policy remains firmware-enforced: attached-default or unknown mode keeps RGB off/strongly limited; 1.5 A allows reduced brightness with serialized high-current loads; 3 A permits full mode with RGB current limiting. Full mode is never enabled from VBUS presence alone.
ERC exception
The imported XIAO symbol types the external VBAT battery pad as a power input. Official Seeed circuitry shows it is the optional charger/battery node. This design intentionally has no battery and the pad is marked no-connect. Flux's Missing Power checker still reports
U1:VBAT; this is a single documented imported-part pin-type false positive. The pad must not be connected to 3.3 V or VBUS merely to silence ERC.Status
- Two expanders and matrix wiring: complete.
- GPIO map: complete.
- 3.3 V peripheral buck: complete.
- Dedicated high-current USB-C input/protection/current detection/priority mux: complete.
- Whole-schematic critical ERC: only documented U1 VBAT imported-pin false positive remains.
- PCB placement, outline, and routing were not changed.
Checklist item 2 — I/O expansion and GPIO map
Final XIAO ESP32-C5 map
Power budget
3.3 V peripheral regulator
Source-mode safety policy
Checklist item 3 — dedicated USB-C input (completed)
ERC exception
Status
