PCB Top Side Placement

Worked for 4 mins 29 sec
Thought for 12 sec
Checking PCB Placement Validation progress…
Thought for 11 sec
Reading PCB Placement Validation's report…
Thought for 13 sec — Verifying information
Getting a layout overview.
Thought for 9 sec
Completed 8 design checks — found 333 issues.
Thought for 14 sec
4/4 Run independent placement and DRC verification

Inspect board outline, stackup, footprints, and fixed constraints

Confirm top-side placement plan and edge assignments

Place all components on the top side and resolve placement violations

Run independent placement and DRC verification

Thought for 13 sec
Thought for 9 sec
Awaiting 1 background task
"PCB Placement Check" completed.

flux

Placed all 62 components on the Top side of the unchanged 90 × 50 mm board. Independent review confirmed no body overlaps, out-of-bounds parts, edge-placement faults, or critical buck-stage findings.
Open items
  • 8 U2/U3 self-keepout false positives from each module intersecting its own antenna void.
  • 12 decoupling proximity warnings and 116 expected airwires remain.
Next steps
  1. Route the board.
  2. Optimize flagged decoupling loops during routing.
  3. Review the detailed Top-Side Placement Validation.
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Schematic

Layout

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Project Specification — UWB Structural Radar
Project Overview
Status: Schematic review
Professional SMD bistatic channel-5 UWB research instrument for structural-void motion sensing. Two independent Qorvo DWM3000TR13 modules are controlled by a dedicated STM32H7A3 MCU; processed detections are reported to an upstream ESP32-S3.
Intended Use
Experimental inspection of non-metallic building structures. This is a research prototype, not a certified imaging or life-safety instrument.
What the Device Should Do
  • Operate U2 as TX and U3 as RX on UWB channel 5.
  • Capture packet-associated RX CIR data over dedicated DMA-capable SPI2.
  • Average frames, subtract static clutter, detect persistent motion energy, and report compact results.
  • Provide baseline 3.3 V UART host reporting plus optional SPI and GPIO handshakes.
  • Support SWD/SWO, debug UART, reset/BOOT0 controls, and critical test access.
System Architecture
Diagram



  
    
  
  
    
  











SPI1

SPI2 + DMA

UART baseline / optional SPI








5 V regulated input
2 A PTC + 5 V TVS
LMR33630B 3 A buck
3.3 V rail
STM32H7A3Vx LQFP100
DWM3000 TX
DWM3000 RX
Upstream ESP32-S3
Selected Hardware

Table

FunctionSelected part
Processing MCUST STM32H7A3V_G-I_Tx, LQFP100, 280 MHz, ~1.18 MB SRAM
UWB TX/RX2× Qorvo DWM3000TR13 antenna modules
3.3 V regulatorTI LMR33630BDDAR, 1.4 MHz, 3 A synchronous buck
HSE clockNDK STDCRA3-8M (NX3225GD family), 8 MHz, 8 pF load, correctly modeled P1/P2 electrodes
Input protectionNANOSMDC200F-2 2 A PTC + SMF5.0A TVS
Interfaces and Connections
  • TX radio: SPI1 PA5/PA6/PA7, CS PA4, IRQ PC4, reset PD0, wake PD2, sync PA0.
  • RX radio: SPI2 PB10/PB14/PB15, CS PB9, IRQ PC5, reset PD1, wake PD3, sync PA1.
  • Host J3: 3V3, GND, USART1 TX/RX on PB6/PB7, HOST_IRQ PB8, HOST_READY PB11, optional SPI3 PC10/PC11/PC12 + PA15 CS.
  • Debug: 10-pin Cortex SWD with SWDIO, SWCLK, SWO, NRST; J4 debug UART on PD8/PD9 plus radio sync/IRQ and power-good signals.
Power Tree and Budget
See the persistent Power Budget and Design Notes file for evidence and calculations. Design estimate is 402 mA peak on 3.3 V and approximately 295 mA from 5 V at 90% efficiency. The 3 A regulator and 2 A protected input path provide large research/transient margin.
Datasheet Support Implemented
  • All STM32 VDD/VSS pins, one 100 nF capacitor per VDD pin, VDDA/VREF 100 nF + 1 uF, VBAT bypass, and two independent 2.2 uF VCAP capacitors.
  • 8 MHz HSE using Y1 STDCRA3-8M with two 10 pF C0G load capacitors. Values use C=2×(CL−Cstray), CL=8 pF and assumed total stray capacitance of 3 pF; NRST 10 kΩ/100 nF and switch; BOOT0 10 kΩ pull-down and switch.
  • Each DWM3000 has all supply/ground pins connected, one 100 nF per supply pin, 10 uF local bulk, CS pull-up, WAKE pull-down, and independent control nets.
  • LMR33630B uses datasheet 1.4 MHz 3.3 V network: 2.2 uH, 10 uF + 220 nF input, 100 nF bootstrap, 1 uF VCC, 4×22 uF output, 100 kΩ/43.2 kΩ feedback, 100 kΩ PG pull-up.
Manufacturing and Physical Expectations
  • SMD professional prototype; four-layer PCB recommended.
  • Preserve Qorvo antenna keepout geometry and keep TX/RX antenna regions physically independent.
  • PCB layout has intentionally not been started.
Assumptions
  • External input is regulated 5 V.
  • Host logic is 3.3 V.
  • STM32 internal LDO mode is used, requiring both 2.2 uF VCAP capacitors.
  • Y1 is STDCRA3-8M with equivalent terminals P1/P2. C19/C20 are 10 pF based on CL=8 pF and an explicit 3 pF total stray-capacitance assumption; validate during clock characterization.
Success Criteria
Complete meaningful netlist, power and ground coverage, support passives and no-connect markings, then clean/justified ERC before PCB layout.
Change Notes
  • Selected actual sourceable DWM3000TR13, STM32H7A3Vx, and LMR33630BDDAR parts.
  • Completed power, dual-radio, host, debug, clock, reset/boot, indicators, and test-point circuitry.
  • Replaced the mis-modeled crystal symbol with sourceable NDK STDCRA3-8M while preserving HSE_IN/HSE_OUT connectivity.

  • Project Overview

  • Intended Use

  • What the Device Should Do

  • System Architecture

  • Selected Hardware

  • Interfaces and Connections

  • Power Tree and Budget

  • Datasheet Support Implemented

  • Manufacturing and Physical Expectations

  • Assumptions

  • Success Criteria

  • Change Notes