Electrical Verification

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Routing requires Agent mode to inspect the updated PCB, check routing feasibility, route all nets, and verify remaining airwires/DRC.

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Understood: routing only—no component placement or movement. Switch to Agent mode to route the existing placement and verify all airwires and routing DRC.
Continue in Agent Mode

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I’ll preserve the current placement, run a routing feasibility check, route the board, then verify remaining airwires and routing DRC.

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Auto-routing converged with the existing placement: all nets are routed. I’m running the final airwire and DRC verification now; no components were moved.

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Board routing completed without moving components.
  • 0 airwires
  • 0 dangling traces
  • No routing-related DRC errors or warnings
  • Auto-router noted one skipped decoupling-routing preference on GND, but the net is fully routed and DRC-clean.
Review route quality
Clean up decoupling
Manufacturing readiness
Export fabrication files
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Files

Schematic

Layout

Preview

Firmware Getting Started
Pin Mapping

Table

FunctionESP32 GPIOSchematic net
PS2 DAT19PS2_DAT
PS2 CMD23PS2_CMD
PS2 ATT27PS2_ATT
PS2 CLK18PS2_CLK
Left throttle DAC25LDAC_RAW
Right throttle DAC26RDAC_RAW
Left forward21LF_CMD
Left reverse22LR_CMD
Right forward32RF_CMD
Right reverse33RR_CMD
Startup Sequence
  1. Configure GPIO21/22/32/33 as outputs and drive all low before initializing other peripherals.
  2. Set DAC25 and DAC26 to zero.
  3. Initialize PS2 bit-banged interface on GPIO19/23/27/18.
  4. Validate controller packets before enabling direction or throttle output.
  5. Apply deadband, range checking, timeout, and break-before-make direction logic.
Safety Behavior
  • Any invalid/stale PS2 packet: both DACs zero and all direction GPIOs low.
  • Never assert forward and reverse for the same controller simultaneously.
  • Insert a configurable all-open dwell before changing direction.
ESP-IDF / Arduino Notes
  • GPIO25 and GPIO26 are the original ESP32 DAC channels.
  • Direction GPIOs should be initialized low at the earliest startup point.
  • Because the hardware analog gain is 1.30 and connector loading yields approximately 1.287 V/V, calibrate output limits against measured TP8/TP9 voltage rather than assuming ideal DAC full scale.

  • Pin Mapping

  • Startup Sequence

  • Safety Behavior

  • ESP-IDF / Arduino Notes