TPS54336A (TPS54336ADRCR) - Calculation Proof of Work (24 V -> 5 V, 0.1 A to 2 A)
This document re-derives the key peripheral component calculations from the TPS54336A datasheet PDF provided by the user and checks them against the values currently set in the schematic.
1) Design targets (given)
- VIN range: 23 V to 25 V (24 V nominal)
- VOUT: 5.0 V
- IOUT range: 0.1 A to 2.0 A
- Load steps: 300 mA steps up to 2 A
- Allowed output ripple: VSENSE) and lower resistor = RFBB (VSENSE->GND):
VOUT = VREF x (RFBT/RFBB + 1)
2.2 Switching frequency
From datasheet:
- "The TPS54336A device has a fixed 340-kHz switching frequency."
- Internal switching frequency (TPS54336A): 272 kHz (min), 340 kHz (typ), 408 kHz (max)
2.3 Inductor selection
From datasheet (as extracted):
VOUT * (VIN(MAX) - VOUT)
L = ----------------------
VIN(MAX) * KIND * IOUT(MAX) * fSW
And:
- KIND is a coefficient representing inductor ripple current relative to maximum output current.
- Guideline: for low-ESR output capacitors (ceramics), KIND = 0.3 can be used; for higher ESR caps, KIND = 0.2 yields better results.
2.4 Output ripple constraints
From datasheet (as extracted):
Capacitive term minimum output capacitance requirement:
I_ripple > 8 * fSW * COUT * VOUT(ripple)
ESR term maximum ESR requirement:
RESR maximum input voltage.
- Some bulk capacitance may be needed, especially if not located within about 2 inches from the input voltage source.
2.6 Bootstrap capacitor recommendation
From datasheet (as extracted):
- Bootstrap capacitor value must be 0.1 uF
- Located between PH and BOOT
- X7R/X5R recommended, voltage rating 10 V or higher
2.7 Soft-start capacitor equation
From datasheet (as extracted):
CSS(nF) * VREF(V) / ISS(uA) = tSS(ms)
Where:
- ISS (TPS54336A) = 2.3 uA
- VREF = 0.8 V
2.8 Compensation example values (5 V output baseline)
From datasheet (as extracted):
- For a 5 V output example design (TPS54335A/TPS54336A family):
- R3 = 3.74 kOhm
- C4 = 0.012 uF
- C5 = 120 pF
3) Values currently in the schematic (for cross-check)
- Switching frequency: TPS54336A fixed (no RT part present)
- RFBT = 220 kOhm
- RFBB = 43.2 kOhm
- L = 15 uH
- CIN: 0.1 uF + 10 uF + 10 uF + 100 uF bulk
- COUT: 47 uF + 47 uF + 0.1 uF
- CBOOT = 0.1 uF
- CSS = 10 nF
- COMP: RCOMP = 3.74 kOhm, CCOMP1 = 12 nF, CCOMP2 = 120 pF
4) Re-calculations and checks
All calculations below use:
- VIN(MAX) = 25 V
- VOUT = 5 V
- IOUT(MAX) = 2 A
- fSW(TYP) = 340 kHz (fixed)
- VOUT(ripple) allowed = 0.25 V
4.1 Feedback divider check (RFBT/RFBB)
Equation:
VOUT = 0.8 * (RFBT/RFBB + 1)
With RFBT = 220k, RFBB = 43.2k:
- RFBT/RFBB = 220k / 43.2k = 5.09259259
- VOUT = 0.8 * (5.09259259 + 1) = 4.87407407 V
Result:
- The current divider does NOT set exactly 5.00 V; it sets ~4.87 V.
Required ratio for 5.00 V:
- 5.00 / 0.8 - 1 = 5.25
- Therefore RFBT/RFBB must equal 5.25
Example fixes (choose one):
- Keep RFBB = 43.2k -> RFBT target = 43.2k * 5.25 = 226.8k
- Keep RFBT = 220k -> RFBB target = 220k / 5.25 = 41.9k
4.2 Inductor value check
Datasheet suggests choosing KIND; for ceramic output caps, KIND = 0.3 is allowed.
Compute L required for KIND = 0.3:
L = VOUT*(VIN(MAX)-VOUT) / (VIN(MAX)KINDIOUT(MAX)fSW)
L = 5(25-5) / (250.32*340k)
L = 1.96078431e-5 H = 19.6078431 uH
Compare to schematic:
- Schematic L = 15 uH (lower than 19.6 uH)
Compute ripple current with L = 15 uH at VIN=25, VOUT=5:
DeltaIL = VOUT*(VIN - VOUT) / (VIN * L * fSW)
DeltaIL = 5*(25-5) / (25 * 15uH * 340k)
DeltaIL = 0.78431373 A p-p
Equivalent KIND actually implemented:
KIND_actual = DeltaIL / IOUT(MAX) = 0.7843 / 2 = 0.39215686
Result:
- L=15 uH corresponds to KIND ~0.392 (39% ripple) at VIN=25 V, fSW=340 kHz.
- This differs from the earlier design intent KIND=0.3; it is still potentially workable, but it changes ripple, RMS currents, and compensation assumptions.
4.3 Output capacitor minimum (ripple-capacitive term)
From datasheet: I_ripple > 8fSWCOUTV_ripple
Rearrange: COUT > I_ripple / (8fSW*V_ripple)
If using KIND=0.3 (design target), I_ripple = KIND*IOUT(MAX) = 0.6 A
COUT_min = 0.6 / (8 * 340k * 0.25)
COUT_min = 8.82352941e-7 F = 0.882352941 uF
Schematic COUT effective:
- Nominal sum = 47 uF + 47 uF + 0.1 uF = 94.1 uF
Result:
- Even with MLCC DC bias derating, output capacitance is far above the datasheet minimum for the ripple equation as extracted.
4.4 Output capacitor ESR limit (ripple-ESR term)
From datasheet: RESR ~3.48 ms)
- Input noise: qualitative PASS directionally (10 uF ceramics + bulk 100 uF + TVS). Cable length suggests bulk is reasonable.
6) Action items implied by this proof
- Adjust the feedback divider to hit 5.00 V exactly (choose standard values that satisfy RFBT/RFBB = 5.25).
- Decide whether to keep L=15 uH (higher ripple, possibly better transient, higher ripple current) or move closer to ~19.6 uH to align with KIND=0.3.
- If L or output cap effective capacitance/ESR differ materially from the datasheet example, revisit compensation (the current network matches the datasheet 5 V example values, but loop may need re-tune if the power stage differs).