High-Level Block Diagram Creation
U_DCDC_5V、U_DCDC_3V3、U7 增加VCC旁路电容:
C_VCC_5V:U_DCDC_5V:VCC → ADC_5V_VCC_BYPASS,电容另一端 → GNDC_VCC_3V3:U_DCDC_3V3:VCC → ADC_3V3_VCC_BYPASS,电容另一端 → GNDC_VCC_U7:U7:VCC → PWR_5V_VCC_BYPASS,电容另一端 → GNDU7 增加BOOT/SW基础外围:
C_BOOT_U7 between PWR_5V_BOOT and PWR_5V_SWU7:BOOT → PWR_5V_BOOTU7:SW + L1:P1 → PWR_5V_SWL1:P2 → PWR_3V3U7:EN → PWR_VINU7:FB → PWR_5V_FB named review netU6 / LM5013DDAR 建立剩余审查网络:
U6:BST → LM5013_BSTU6:SW → LM5013_SWU6:FB → LM5013_FBU6:RON → LM5013_RONU6:EN/UVLO → PWR_VINERROR / WARNING / OPEN 项。LM5013_* 和 PWR_5V_FB 是保留给后续datasheet精确外围/分压/频率设定审查的命名网络。本轮目标
已完成的Schematic修改
ERC结果
注意事项
下一步建议