High-Level Block Diagram Creation


Create a high level mermaid block diagram of this project. Include key component's manufacturer part number in each block whenever possible.
I’ll inspect the project structure and BOM, then create a concise high-level Mermaid block diagram document with MPNs where available.
I found the major blocks: RP2350 MCU, power tree, M40 interface, XY2/encoder DB25, laser safety, I2C expanders, isolated digital I/O, and analog ADS8688-LZM8688 interface. I’m saving the diagram as a project document now.
Created the high-level Mermaid block diagram and saved it in High Level Block Diagram. It includes the main functional blocks and key MPNs from the schematic/BOM, with caveats for connector-only or ambiguous regulator entries.
Review diagram and ERC
Run schematic ERC
Fix ambiguous MPNs
Create power tree
Check BOM risk
Explain block diagram

U1
Q1
U4
U8
U6
LM5013_RON
U7 VCC - C_VCC_U7 P1
Q1 G - U8 GATE
M40_PIN_33
U1 QSPI_SD1 - U2 DO(IO1)
U6 VIN - U8 CATHODE
U6 VIN - U8 CATHODE
U_ENC SW - C_BOOT_ENC P2
U1 QSPI_SS - U2 ~{CS}
U1 GPIO18 - U25 4A
U1 RUN - U4 ~{RESET}
U1 QSPI_SS - U2 ~{CS}
U1 QSPI_SD3 - U2 HOLD#orRESET#(IO3)
U6 VIN - U8 CATHODE
Q1 D - Q1 D
U_ENC VBST - C_BOOT_ENC P1
U1 QSPI_SD0 - U2 DI(IO0)
U1 IOVDD - U1 QSPI_IOVDD
M40_WE
U1 GPIO12 - U25 1A
M40_PIN_30
U1 IOVDD - U1 QSPI_IOVDD
LM5013_FB
U1 GPIO16 - U25 3A
M40_PIN_32
U7 SW - C_BOOT_U7 P2
MB_XY2_CLK_N_UNUSED_DOC
M40_PIN_35
U1 GPIO8 - U4 WDI
U6 VIN - U8 CATHODE
U1 QSPI_SCLK - U2 CLK
U1 QSPI_SD3 - U2 HOLD#orRESET#(IO3)
U_ISO VCC1 - R_PU_INTERLOCK P1
U9 1Y - U1 GPIO20
F1 1 - Q1 S
U1 IOVDD - U1 QSPI_IOVDD
MB_PSO_TRIGGER
U9 2Y - U1 GPIO21
U_ISO VCC1 - R_PU_INTERLOCK P1
U1 QSPI_SD2 - U2 WP#(IO2)
U1 GPIO14 - U25 2A
U1 QSPI_SD2 - U2 WP#(IO2)
PWR_IDEAL_DIODE_VCAP
U_ENC EN - R_ENC_EN P1
PWR_5V
Q1 G - U8 GATE
U10 1Y - U1 GPIO22
U1 GPIO8 - U4 WDI
U1 GPIO26 - U18 A
M40_IRQ
RP2350_VREG_LX
U1 GPIO5 - U3 SCK
U10 2Y - U1 GPIO23
U1 GPIO10 - U_ISO IN
M40_PIN_28
MB_XY2_Y_N_UNUSED_DOC
F1 1 - Q1 S
PWR_5V_FB
U1 QSPI_SD0 - U2 DI(IO0)
U_ISO VCC1 - R_PU_INTERLOCK P1
U1 GPIO11 - J_DB25 Pin_20
U1 QSPI_SD1 - U2 DO(IO1)
LM5013_SW
M40_PIN_8
U1 IOVDD - U1 QSPI_IOVDD
R_ENC_FB1 P2 - R_ENC_FB2 P1
RP2350_VREG_FB
U_ISO VCC1 - R_PU_INTERLOCK P1
M40_PIN_34
U1 GPIO4 - U3 SDA
U1 IOVDD - U1 QSPI_IOVDD
MB_XY2_X_N_UNUSED_DOC
LM5013_BST
U7 BOOT - C_BOOT_U7 P1
U1 QSPI_SCLK - U2 CLK
U6 VIN - U8 CATHODE
MB_XY2_SYNC_N_UNUSED_DOC
M40_PIN_31
U1 RUN - U4 ~{RESET}
U6 EP - U7 PGND
U6 EP - U7 PGND
U1 GND - U1 VREG_PGND
GND
U6 EP - U7 PGND
GND
U1 GND - U1 VREG_PGND
U6 EP - U7 PGND
U6 EP - U7 PGND
U6 EP - U7 PGND
U7
U_ENC
U2
Not Recommended for New Designs

LMS controller

LMS controller thumbnail