ESP32 Heater Controller


I’ll re-check the layout after your R4/J7 move, distinguish PCB airwires from actual schematic one-sided wiring, then evaluate whether BOOT/RESET buttons can be removed in favor of ESP32-S3 native USB auto-download behavior.
Done.
Accomplished:
  • Verified RT6/C25, RT4/C23, C14, and related passives are schematic-connected on both sides; the issue was PCB routing/airwires, not one-sided schematic wiring.
  • Removed optional S1 BOOT and S2 RESET buttons to save BOM/assembly cost.
  • Kept the important ESP32 support: R4 GPIO0 pull-up, R3 EN pull-up, and C11 EN reset-delay cap.
  • Cleaned stale routing from your R4/J7 move and re-routed.
  • Final checked categories are clean: no airwires, dangling traces, copper overlaps, invalid layers, or relevant ERC errors.
Open items:
  • If we want best serviceability, add tiny labeled test pads for GPIO0/BOOT and EN/RESET later; they are cheaper than buttons and useful for recovery.
Suggested next steps:
  1. Visually inspect the routed PCB.
  2. Add/verify GND pours and antenna keepout.
  3. Run full manufacturing DRC before export.
  4. Update firmware/bring-up docs to note USB flashing without BOOT/RESET buttons.
Pours, keepout, docs
Add test pads
Verify GND pours
Check antenna keepout
Update docs
Manufacturing review

J1
U3
U2
U5
L1 P2 - U3 FB
U2 VBUS_EN_SNK - R9 P2
J1 DP2 - U5 I/O1
U1 TXD0 - J7 3
U1 IO18 - SW1 B
U1 IO8 - U2 SCL
J1 VBUS_B - C1 P1
U1 IO8 - U2 SCL
U4 DV/DT - C4 P1
Q1 D - J2 2
U1 IO1 - R30 P2
U1 IO4 - R33 P2
U1 IO3 - R32 P2
U1 IO13 - R23 P1
U2 VREG_1V2 - C12 P1
L1 P2 - U3 FB
J1 DP2 - U5 I/O1
U1 IO6 - R35 P2
Q3 D - J4 2
U4 EN - R2 P2
U1 IO16 - R42 P1
U1 RXD0 - J7 4
L1 P2 - U3 FB
U1 IO19 - J1 DN1
U1 IO4 - R33 P2
U1 IO2 - R31 P2
U1 IO9 - U2 SDA
J1 VBUS_B - C1 P1
U1 IO21 - SW1 2
R20 P2 - Q1 G
J1 CC2 - U2 CC2
J1 VBUS_B - C1 P1
J1 CC1 - U2 CC1
L1 P2 - U3 FB
U1 IO6 - R35 P2
U4 ILIMIT - R1 P1
U1 EN - R3 P2
U1 IO18 - SW1 B
J1 CC1 - U2 CC1
U3 SW - L1 P1
L1 P2 - U3 FB
U2 VBUS_EN_SNK - R9 P2
Q1 D - J2 2
U1 IO9 - U2 SDA
U1 IO18 - SW1 B
U1 IO1 - R30 P2
U1 IO2 - R31 P2
Q3 D - J4 2
U1 IO6 - R35 P2
U1 IO8 - U2 SCL
U1 IO5 - R34 P2
U4 SOURCE - C3 P1
U1 IO1 - R30 P2
L1 P2 - U3 FB
U4 SOURCE - C3 P1
U1 TXD0 - J7 3
U3 SW - L1 P1
U1 EN - R3 P2
U1 IO5 - R34 P2
U2 ALERT - R8 P2
U1 IO10 - R20 P1
L1 P2 - U3 FB
U1 IO5 - R34 P2
R21 P2 - Q2 G
U1 IO14 - R40 P1
U2 VBUS_VS_DISCH - R5 P2
U1 IO3 - R32 P2
Q2 D - J3 2
J1 VBUS_B - C1 P1
U1 RXD0 - J7 4
U1 IO5 - R34 P2
U1 IO19 - J1 DN1
R22 P2 - Q3 G
U1 IO10 - R20 P1
U1 IO21 - SW1 2
U1 IO21 - SW1 2
J1 VBUS_B - C1 P1
Q4 D - J5 2
R20 P2 - Q1 G
J1 CC2 - U2 CC2
U4 SOURCE - C3 P1
U2 ALERT - R8 P2
L1 P2 - U3 FB
U1 IO6 - R35 P2
U1 IO17 - SW1 A
U1 IO17 - SW1 A
L1 P2 - U3 FB
R21 P2 - Q2 G
L1 P2 - U3 FB
U1 IO9 - U2 SDA
R41 P2 - D3 K
U1 IO19 - J1 DN1
U4 SOURCE - C3 P1
U4 SOURCE - C3 P1
U1 IO2 - R31 P2
L1 P2 - U3 FB
L1 P2 - U3 FB
L1 P2 - U3 FB
U1 IO11 - R21 P1
L1 P2 - U3 FB
L1 P2 - U3 FB
U1 IO4 - R33 P2
U1 IO17 - SW1 A
R42 P2 - D4 K
L1 P2 - U3 FB
R22 P2 - Q3 G
J1 VBUS_B - C1 P1
R40 P2 - D2 K
U1 IO8 - U2 SCL
J1 CC2 - U2 CC2
J1 VBUS_B - C1 P1
R23 P2 - Q4 G
J1 VBUS_B - C1 P1
L1 P2 - U3 FB
U2 VREG_2V7 - C13 P1
U1 IO19 - J1 DN1
U1 IO11 - R21 P1
U1 EN - R3 P2
U1 IO1 - R30 P2
U1 IO3 - R32 P2
U1 IO0 - R4 P2
U1 IO15 - R41 P1
L1 P2 - U3 FB
U1 IO12 - R22 P1
U1 IO20 - J1 DP1
U4 SOURCE - C3 P1
J1 VBUS_B - C1 P1
U4 SOURCE - C3 P1
U4 SOURCE - C3 P1
U1 IO3 - R32 P2
L1 P2 - U3 FB
U2 ALERT - R8 P2
U1 IO16 - R42 P1
U3 SW - L1 P1
U1 IO20 - J1 DP1
R41 P2 - D3 K
U4 SOURCE - C3 P1
R23 P2 - Q4 G
U4 ILIMIT - R1 P1
Q2 D - J3 2
R20 P2 - Q1 G
U2 VREG_2V7 - C13 P1
L1 P2 - U3 FB
U1 IO2 - R31 P2
U4 EN - R2 P2
R21 P2 - Q2 G
L1 P2 - U3 FB
R22 P2 - Q3 G
J1 VBUS_B - C1 P1
R40 P2 - D2 K
U3 BST - C8 P1
U4 DV/DT - C4 P1
U3 BST - C8 P1
L1 P2 - U3 FB
U1 IO0 - R4 P2
L1 P2 - U3 FB
U1 IO13 - R23 P1
L1 P2 - U3 FB
U1 IO17 - SW1 A
U2 VREG_1V2 - C12 P1
U1 IO19 - J1 DN1
U1 IO12 - R22 P1
R42 P2 - D4 K
U1 IO21 - SW1 2
U2 VBUS_VS_DISCH - R5 P2
R23 P2 - Q4 G
J1 DP2 - U5 I/O1
L1 P2 - U3 FB
U1 IO9 - U2 SDA
L1 P2 - U3 FB
J1 CC1 - U2 CC1
U1 IO18 - SW1 B
J1 VBUS_B - C1 P1
U1 IO4 - R33 P2
U1 IO15 - R41 P1
Q4 D - J5 2
L1 P2 - U3 FB
U1 IO14 - R40 P1
Q1 S - Q2 S
Q1 S - Q2 S
RT1 2 - RT2 2
SW1 C - C50 P2
J1 SHIELD - C1 P2
Q1 S - Q2 S
U2 EP - U2 VSYS
J1 SHIELD - C1 P2
J1 SHIELD - C1 P2
GND
C6 P2 - C7 P2
Q1 S - Q2 S
Q1 S - Q2 S
U2 EP - U2 VSYS
RT1 2 - RT2 2
RT1 2 - RT2 2
RT1 2 - RT2 2
RT1 2 - RT2 2
J1 SHIELD - C1 P2
C6 P2 - C7 P2
SW1 C - C50 P2
RT1 2 - RT2 2
RT1 2 - RT2 2
SW1 C - C50 P2
U1 GND_11 - J6 1
Q1 S - Q2 S
Q1 S - Q2 S
C6 P2 - C7 P2
SW1 C - C50 P2
C6 P2 - C7 P2
C6 P2 - C7 P2
C6 P2 - C7 P2
J1 SHIELD - J1 SHIELD
U2 EP - U2 VSYS
J1 SHIELD - J1 SHIELD
GND
J1 SHIELD - C1 P2
Q1 S - Q2 S
J1 SHIELD - C1 P2
SW1 C - C50 P2
RT1 2 - RT2 2
SW1 C - C50 P2
SW1 C - C50 P2
GND
J1 SHIELD - C1 P2
C6 P2 - C7 P2
J1 SHIELD - C1 P2
RT1 2 - RT2 2
U2 EP - U2 VSYS
C6 P2 - C7 P2
C6 P2 - C7 P2
C6 P2 - C7 P2
RT1 2 - RT2 2
J1 SHIELD - C1 P2
J1 SHIELD - C1 P2
J1 SHIELD - C1 P2
RT1 2 - RT2 2
C6 P2 - C7 P2
GND
RT1 2 - RT2 2
U2 EP - U2 VSYS
U1 GND_11 - J6 1
R42
Resistance
220Ω
C24
Capacitance
100nF
R33
Resistance
10kΩ
R5
Resistance
470Ω
C25
Capacitance
100nF
R27
Resistance
100kΩ
C1
Capacitance
10uF
R8
Resistance
4.7kΩ
C21
Capacitance
100nF
D3
C9
Capacitance
100nF
RT2
Resistance
10kΩ
C4
Capacitance
47nF
R41
Resistance
220Ω
RT6
Resistance
10kΩ
R52
Resistance
10kΩ
C13
Capacitance
1uF
R40
Resistance
560Ω
R3
Resistance
10kΩ
R24
Resistance
100kΩ
R51
Resistance
10kΩ
C22
Capacitance
100nF
R1
Resistance
1.1kΩ
C12
Capacitance
1uF
C23
Capacitance
100nF
R30
Resistance
10kΩ
R32
Resistance
10kΩ
C50
Capacitance
10nF
C11
Capacitance
1uF
RT1
Resistance
10kΩ
C20
Capacitance
100nF
C5
Capacitance
10uF
C8
Capacitance
100nF
R7
Resistance
4.7kΩ
C3
Capacitance
10uF
C14
Capacitance
100nF
C6
Capacitance
22uF
RT5
Resistance
10kΩ
C7
Capacitance
22uF
R6
Resistance
4.7kΩ
R31
Resistance
10kΩ
R50
Resistance
10kΩ
C15
Capacitance
100nF
C2
Capacitance
1uF
R20
Resistance
100Ω
C52
Capacitance
100nF
R34
Resistance
10kΩ
RT3
Resistance
10kΩ
R9
Resistance
100kΩ
R23
Resistance
100Ω
R35
Resistance
10kΩ
R2
Resistance
300kΩ
R4
Resistance
10kΩ
C10
Capacitance
10uF
D2
C51
Capacitance
10nF
RT4
Resistance
10kΩ
R25
Resistance
100kΩ
R21
Resistance
100Ω
R26
Resistance
100kΩ
R22
Resistance
100Ω
U1
Q1
J2
J3
J5
Q4
D4
Q3
DS1
Q2
J4
U4
L1
Inductance
4.7µH
J7
D1
SW1
Board Bring-Up Plan — ESP32 Heater Controller
Prerequisites
Equipment:
  • Current-limited bench supply, DMM, oscilloscope, USB-C current/PD analyzer if available
  • Thermal camera or thermocouples for MOSFETs, MP5036, AP63203, heater connectors, enclosure hot spots
  • 25 Ω, >=5 W dummy loads for each 5 V / 1 W heater channel
  • Computer with PlatformIO and USB serial monitor
Critical safety note: Do not first-power this board from a PD-capable charger until STUSB4500 NVM is proven 5 V-only. A factory/default STUSB4500 configuration can request higher-voltage PDOs, which would be destructive because the downstream rail is designed as 5 V.
1. Visual Inspection
  • Inspect USB-C pins on J1 for bridges and shell shorts.
  • Inspect U2 STUSB4500, U4 MP5036, U3 AP63203, U1 ESP32-S3 module, Q1-Q4 MOSFET orientation, and all polarized parts.
  • Confirm heater terminal blocks J2-J5 are oriented consistently and soldered cleanly.
  • Confirm no metal debris near USB-C, heater terminals, or buck converter.
  • Confirm ESP32 antenna edge/keepout is respected once layout is complete.
2. Power Rail Verification

Table


RailSourceExpected VoltageToleranceMeasure AtInitial Current LimitPass Criteria
VBUS_RAWUSB-C J1 / bench supply5.0 V+/-5%J1 VBUS, U4 VIN50-100 mA logic-onlyStable 5 V, no overheating
5V_PROTECTEDU4 MP5036 eFuse output5.0 V minus small drop+/-5%J2-J5 pin 1, U3 VIN50-100 mA first, then stagedTracks VBUS, no eFuse cycling
3V3U3 AP63203 buck output3.3 V+/-5%U1 3V3, J6 pin 2, J7 pin 250-100 mA first3.135-3.465 V, low ripple
STUSB_VREG_2V7U2 internal regulator~2.7 VDatasheet limitU2 decoupling capLogic-onlyPresent when U2 powered
STUSB_VREG_1V2U2 internal regulator~1.2 VDatasheet limitU2 decoupling capLogic-onlyPresent when U2 powered
Procedure:
  1. With power off, measure resistance from VBUS_RAW, 5V_PROTECTED, and 3V3 to GND.
  2. Measure each HEATERx_LOW node to GND and to 5V_PROTECTED to catch MOSFET or connector shorts.
  3. Leave all heaters disconnected for first power.
  4. Apply 5.0 V from a current-limited bench supply or known non-PD 5 V USB source.
  5. Start at 50-100 mA. If rails are valid, increase to 200 mA, 500 mA, 1 A, 1.5 A, and only later 2 A.
  6. Verify U4 current limit behavior near the design target (~2 A from R1 = 1.1 kΩ) only with dummy loads and thermal monitoring.
3. Critical Signal Verification

Table


SignalNetExpected StateMeasure AtNotes
ESP32 enableESP_ENHigh during run, low when S2 pressedU1 ENR3 10k pull-up, C11 reset cap
ESP32 bootESP_BOOTHigh during normal boot, low when S1 pressedU1 GPIO0R4 10k pull-up
Heater gate 1HEATER1_GATE / HEATER1_PWMLow at reset and bootQ1 gate, U1 GPIO10Verify no ROM boot pulse turns heater on
Heater gate 2HEATER2_GATE / HEATER2_PWMLow at reset and bootQ2 gate, U1 GPIO11Verify no ROM boot pulse turns heater on
Heater gate 3HEATER3_GATE / HEATER3_PWMLow at reset and bootQ3 gate, U1 GPIO12Verify no ROM boot pulse turns heater on
Heater gate 4HEATER4_GATE / HEATER4_PWMLow at reset and bootQ4 gate, U1 GPIO13Verify no ROM boot pulse turns heater on
I2CI2C_SCL/I2C_SDAIdle high at 3.3 VJ6 pins 4/3R7/R6 4.7k pull-ups
PD alertPD_ALERTNormally high, low on alertU1 GPIO38 / U2 ALERTR8 4.7k pull-up
Procedure:
  1. Scope all heater PWM/gate pins during power ramp, reset button press, bootloader entry, firmware upload, brownout, and eFuse recovery.
  2. Confirm firmware initializes GPIO10-GPIO13 low before any heater is connected.
  3. Confirm I2C bus idles high and scans U2 STUSB4500 at expected address 0x28.
4. Connector and Interface Tests

Table


ConnectorTypePins to VerifyTest Method
J1USB-CVBUS_RAW, GND, CC1/CC2, USB_D_P/NContinuity, USB enumeration, ESD part orientation
J2Heater 1 terminal5V_PROTECTED, HEATER1_LOWDummy load at 25 Ω, PWM test
J3Heater 2 terminal5V_PROTECTED, HEATER2_LOWDummy load at 25 Ω, PWM test
J4Heater 3 terminal5V_PROTECTED, HEATER3_LOWDummy load at 25 Ω, PWM test
J5Heater 4 terminal5V_PROTECTED, HEATER4_LOWDummy load at 25 Ω, PWM test
J6Qwiic I2CGND, 3V3, SDA, SCLI2C scan, OLED/display test
J7UART/debugGND, 3V3, TXD0, RXD03.3 V UART echo/debug
5. Programming and Debug Interface

Table


InterfaceSignalsConnectorTool
Native USBUSB_D_P, USB_D_NJ1 USB-CPlatformIO / esptool
Boot buttonsESP_BOOT, ESP_ENS1, S2Manual bootloader entry
UART fallbackUART_TXD0, UART_RXD0J73.3 V USB-UART adapter
Procedure:
  1. Power board at 5 V current-limited, heaters disconnected.
  2. Flash safe firmware that initializes all heater pins low.
  3. If USB enumeration fails, hold S1/BOOT, press and release S2/EN, then release S1.
  4. Confirm serial output at 115200 baud.
  5. Confirm I2C scan reports STUSB4500 and any display connected to J6.
6. Functional Validation

Table


TestComponentsInputExpected OutputPass Criteria
Safe bootU1, Q1-Q4Power cycle/resetHeater PWM lowAll heater gates remain low
NTC readbackRT1-RT6Room temperaturePlausible ADC temperaturesAll readings within room temp +/- expected tolerance
NTC fault openRT1-RT6Simulate openFault stateHeaters disabled/latch off
NTC fault shortRT1-RT6Simulate short to GNDFault stateHeaters disabled/latch off
EncoderSW1Rotate/pushCounts/button state changesNo false stuck state
LEDsD2-D4Firmware color testRGB indicatorsCorrect active-low behavior
Heater channel 1Q1/J225 Ω dummy loadPWM current modulation0%, 10%, 50%, 100% work
Heater channel 2Q2/J325 Ω dummy loadPWM current modulation0%, 10%, 50%, 100% work
Heater channel 3Q3/J425 Ω dummy loadPWM current modulation0%, 10%, 50%, 100% work
Heater channel 4Q4/J525 Ω dummy loadPWM current modulation0%, 10%, 50%, 100% work
All heatersQ1-Q4/J2-J5Four dummy loads~0.8 A heater loadRails stable, components cool
WiFi loadU1WiFi activeNo brownout3V3 stable during RF peaks
PD 5 V sourceU2/J1PD charger after NVM verification5 V contract onlyVBUS remains 5 V
7. Expected Measurements Reference

Table


MeasurementLocationExpected ValueInstrument
USB inputVBUS_RAW to GND5.0 VDMM/scope
Protected heater rail5V_PROTECTED to GND~5.0 VDMM/scope
Logic rail3V3 to GND3.3 VDMM/scope
Heater current per channelJ2-J5 with 25 Ω load~200 mA at 100%DMM/current probe
Total heater current5V_PROTECTED source~800 mA at 4 channels 100%Current probe/supply
MOSFET temperatureQ1-Q4Comfortably below package limitThermal camera
eFuse temperatureU4No thermal cycling at normal loadThermal camera
Buck temperatureU3/L1Stable under WiFi/display loadThermal camera
8. Destructive-Risk Tests to Run Carefully
Use current-limited supply and dummy loads first:
  • 0.5 A, 0.9 A, 1.5 A, and 2.0 A source limit behavior.
  • Heater connector short to GND.
  • MOSFET drain-source short simulation.
  • Long heater leads with PWM to observe ringing/EMI.
  • Unplug/replug USB with heaters previously commanded on.
  • Brownout/eFuse cycling recovery.
Pass/Fail Summary

Table


Test SectionResultNotes
Visual Inspection[ ] Pass / [ ] Fail
Power Rails[ ] Pass / [ ] Fail
Critical Signals[ ] Pass / [ ] Fail
Connectors[ ] Pass / [ ] Fail
Programming[ ] Pass / [ ] Fail
Functional Validation[ ] Pass / [ ] Fail
Thermal Validation[ ] Pass / [ ] Fail
Fault Tests[ ] Pass / [ ] Fail
Board Status: [ ] Ready for deployment / [ ] Requires rework
  • Prerequisites

  • 1. Visual Inspection

  • 2. Power Rail Verification

  • 3. Critical Signal Verification

  • 4. Connector and Interface Tests

  • 5. Programming and Debug Interface

  • 6. Functional Validation

  • 7. Expected Measurements Reference

  • 8. Destructive-Risk Tests to Run Carefully

  • Pass/Fail Summary