# Zoophagous Amaranth Electromagnetic Shrinking Machine ## Description Compact USB-C BLE Dongle with Integrated USB Device Support ## Project Details - **Owner:** rintoj - **Created:** 10/7/2025 - **Last Updated:** 10/7/2025 - **Visibility:** Public - **layout_review_issues:** Duplicate GND nets found (two separate nets named "GND") — merge into a single ground net to avoid split returns; ensure all shields and GND pins join the same GND net. Place VBUS protection and fuse: locate F1 and required TVS as close as possible to J1 VBUS pads; keep VIN trace from J1 to U2 <5 mm and as wide/short as feasible. USB data routing: route D+ and D- as a controlled-impedance differential pair with matched lengths and consistent spacing; minimize stubs to TVS/CM choke and place TVS with minimal stub. Verify TVS capacitance <1 pF per data line. Common-mode choke and TVS placement: place L1 and D1 immediately after connector on the data lines; keep differential pair routing continuous through L1. Power decoupling and LDO: place C1 (VIN decoupling) and C2 (VOUT decoupling) as close as possible to U2 pins with short traces and ground vias; verify capacitor types/values meet XC6220B331MR datasheet stability requirements. U1 ground/EP: connect the nRF52840 EP (exposed pad) to the GND plane with multiple thermal/ground vias; ensure a continuous ground plane and stitching vias around RF section. Antenna and RF routing: provide antenna keepout, route RF feed from ANT/U.FL as 50 Ω transmission line, avoid ground pours under the antenna, and maintain required clearance from metal and mounting holes. SWD header and programming accessibility: ensure J2 is accessible and SWD traces (SWDIO, SWDCLK, nRESET) are short and free of vias where possible. General layout checks: run ERC/DRC for missing footprints, airwires, overlapping copper, trace-to-pad clearances, minimum trace widths, and verify no copper under antenna keepout. Priority actions: 1) Fix duplicate GND nets (critical). 2) Re-locate/confirm placement of F1, TVS, and L1 at J1 (high). 3) Check LDO decoupling placement and EP stitching (high). 4) Review USB differential pair routing and antenna keepout (high). - **Power Requirements:** USB - **Connectivity:** USB - **Domain:** Consumer Electronics - **Connectivity:** Bluetooth - **Operating Voltage:** 3.3V - **manufacturability_review:** Consolidated manufacturability analysis and prioritized recommendations: 1) Duplicate GND nets: Multiple nets named "GND" exist — merge into a single GND net so all shield and GND pins share the same return. This is critical to avoid split returns and EMI issues. 2) VBUS protection & placement: Place F1 (PTC/fuse) and the dedicated VBUS TVS as close as possible to J1 VBUS pads. Keep the VIN trace from J1 to U2 <5 mm and as short/wide as practical. 3) USB data protection & routing: Ensure bidirectional TVS on D+ and D- has ≤1 pF capacitance per line. Place the common‑mode choke (L1) immediately after J1, with the differential pair routed continuously through it. Minimize stubs to TVS/CM choke. 4) Differential pair integrity: Route D+ / D- as a matched-length controlled-impedance differential pair (target ~90 Ω diff), consistent spacing, length-matched, with no unnecessary vias; verify settled lengths for USB2.0 timing. 5) LDO decoupling & EP stitching: Place VIN decoupling (C1) and VOUT decoupling (C2/C3) immediately adjacent to U2 VIN/VOUT pins with short traces and ground vias. Verify C type/values meet XC6220B331MR stability and transient requirements. Connect U2 exposed pad to ground plane with multiple thermal/ground vias and stitching around RF area. 6) Antenna & RF keepout: Enforce antenna keepout region, route RF feed as a 50 Ω transmission line (microstrip/stripline per stackup), avoid copper pours under antenna, and maintain required clearances from mounting holes and metal. Add stitching vias at ground plane edges near RF as needed. 7) SWD/programming accessibility: Ensure J2 is physically accessible; keep SWDIO, SWDCLK, and nRESET traces short and avoid vias where possible for reliability during programming. 8) Footprints & assembly: Verify all footprints, pad sizes, solder mask, and courtyard clearances for manufacturability; ensure board-edge USB-C mechanical clearance and pick-and-place access; include fiducials. 9) ERC/DRC checks: Run full ERC/DRC for missing footprints, airwires, overlapping copper, trace-to-pad clearances, minimum trace widths, and copper in antenna keepout. Fix high-priority items before fabrication. Prioritized next actions: 1) Merge duplicate GND nets (critical). 2) Re-locate/confirm placement of F1, TVS (VBUS), and L1 at J1 (high). 3) Verify LDO decoupling placement, component values, and EP stitching for U2 (high). 4) Review USB D+/D- differential routing and verify TVS capacitance <1 pF (high). 5) Validate antenna keepout and 50 Ω feed geometry (medium). 6) Run ERC/DRC and iterate on layout to resolve any remaining DRC/assembly issues (medium). End of manufacturability_review. - **Operating Voltage:** 5V ## Key Components ### D1 — [ESD321DPYR](https://www.flux.ai/corvus96/esd321dpyr~2s.md) - Datasheet URL: https://www.ti.com/lit/ds/symlink/esd321.pdf?HQS=dis-dk-null-digikeymode-dsf-pf-null-wwe&ts=1690491326127&ref_url=https%253A%252F%252Fwww.ti.com%252Fgeneral%252Fdocs%252Fsuppproductinfo.tsp%253FdistId%253D10%2526gotoUrl%253Dhttps%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fesd321 - Role Details: Bidirectional TVS diode for USB D+ and D- lines - Role: Protection - Manufacturer Name: Texas Instruments - Manufacturer Part Number: ESD321DPYR - DataLine_Capacitance_Limit: Verify protection capacitance <= 1pF per data line to meet USB2.0 signal integrity requirements; if part exceeds, select lower-capacitance TVS. **Pins:** - GND [pin 2] - IO [pin 1] ### F1 — [0603L050YR](https://www.flux.ai/jecstronic/0603l050yr~fdt.md) - Manufacturer Part Number: 0603L050YR - Role Details: Overcurrent protection for USB VBUS line - Manufacturer Name: Littelfuse Inc. - Part Type: Fuse - License: https://creativecommons.org/licenses/by/4.0/ - Datasheet URL: https://www.mouser.com/datasheet/2/240/media-3321531.pdf - Role: Protection - PTC_Fuse_Review: Required — validate hold/trip currents and inrush behavior for USB bus-power; ensure fuse selection does not prevent regulator startup or normal operation. **Pins:** - P1 [pin 1] - P2 [pin 2] ### J1 — [2024100002](https://www.flux.ai/adrian95/2024100002~atk.md) - Manufacturer Name: Molex - VBUS_Transient_Protection: Required — add dedicated VBUS transient/surge protection (low-leakage, low-capacitance TVS or surge clamp rated for 5V bus) and document recommended part characteristics. - Manufacturer Part Number: 2024100002 - Role Details: USB-C receptacle, USB 2.0 differential data lanes + VBUS/GND - Part Type: Connector - License: https://creativecommons.org/licenses/by/4.0/ - Datasheet URL: https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/834/202410002_Pkg_Spec.pdf - Role: Connector **Pins:** - CC1 [pin A5] - CC2 [pin B5] - DA- [pin A7] - DA+ [pin A6] - DB- [pin B7] - DB+ [pin B6] - GND1 [pin A1] - GND2 [pin A12] - GND3 [pin B1] - GND4 [pin B12] - RX1- [pin B10] - RX1+ [pin B11] - RX2- [pin A10] - RX2+ [pin A11] - SBU1 [pin A8] - SBU2 [pin B8] - SHIELD1 [pin SH1] - SHIELD2 [pin SH2] - SHIELD3 [pin SH3] - SHIELD4 [pin SH4] - TX1- [pin A3] - TX1+ [pin A2] - TX2- [pin B3] - TX2+ [pin B2] - VBUS1 [pin A4] - VBUS2 [pin A9] - VBUS3 [pin B4] - VBUS4 [pin B9] ### J2 — [ARM JTAG SWD 10Pin 0.05" Connector](https://www.flux.ai/vasy_skral/arm-jtag-swd-10pin-005-connector~y0b.md) - Role: Connector - Manufacturer Name: Analog Devices - Role Details: SWD programming/debug header, 10-pin ARM JTAG/SWD 1.27 mm - Datasheet URL: https://suddendocs.samtec.com/catalog_english/ftsh_smt.pdf - Part Type: Connector - Manufacturer Part Number: FTSH-105-01-L-DV-007-K **Pins:** - ~RESET~ [pin 10] - GND [pin 5] - GND [pin 3] - GNDDetect [pin 9] - NC/TDI [pin 8] - SWDCLK/TCK [pin 4] - SWDIO/TMS [pin 2] - SWO/TDO [pin 6] - VTref [pin 1] ### J3 — [U.FL-R-SMT-1(10)](https://www.flux.ai/jecstronic/upfl-r-smt-110~du.md) - License: https://creativecommons.org/licenses/by/4.0/ - Manufacturer Part Number: U.FL-R-SMT-1(10) - Role: Connector - Manufacturer Name: Hirose Electric Co Ltd - Role Details: External antenna connector for BLE SoC - Part Type: Connector - Datasheet URL: https://media.digikey.com/pdf/Data%20Sheets/Hirose%20PDFs/EDC3-302540-10.tif.pdf **Pins:** - Center_Contact [pin 2] - Outer_Contact [pin 1] - Outer_Contact [pin 3] ### U1 — [NRF52840-QIAA-R](https://www.flux.ai/lcsc/nrf52840-qiaa-r~yts0.md) - LCSC Part Number: C190794 - Package or Case Code: AQFN-73_L7.0-W7.0-P0.50-BL-EP4.8 - JLCPCB Part Class: Extended Part - Part Type: RF Transceiver ICs - Role Details: BLE SoC with native USB device support - Product Info Url: https://lcsc.com/product-detail/Others_Nordic-Semicon_NRF52840-QIAA-R_Nordic-Semicon-NRF52840-QIAA-R_C190794.html - Datasheet URL: https://storage.googleapis.com/graviton-electric-symbols/document_assets/lcsc/2304140030_Nordic-Semicon-NRF52840-QIAA-R_C190794.pdf - Role: Main MCU - Manufacturer Part Number: NRF52840-QIAA-R - Manufacturer Name: NORDIC **Pins:** - ANT [pin H23] - D- [pin AD4] - D+ [pin B16] - DCC [pin B3] - DCCH [pin AB2] - DEC1 [pin C1] - DEC2 [pin A18] - DEC3 [pin D23] - DEC4 [pin B5] - DEC5 [pin N24] - DEC6 [pin E24] - DECUSB [pin AC5] - EP [pin 0] - P0.00/XL1 [pin D2] - P0.01/XL2 [pin F2] - P0.02/AIN0 [pin A12] - P0.03/AIN1 [pin B13] - P0.04/AIN2 [pin J1] - P0.05/AIN3 [pin K2] - P0.06 [pin L1] - P0.07/TRACECLK [pin M2] - P0.08 [pin N1] - P0.09/NFC1 [pin L24] - P0.10/NFC2 [pin J24] - P0.11 [pin T2] - P0.12/TRACEDATA1 [pin U1] - P0.13 [pin AD8] - P0.14 [pin AC9] - P0.15 [pin B17] - P0.16 [pin AC11] - P0.17 [pin AD12] - P0.18/nRESET [pin AC13] - P0.19 [pin AC15] - P0.20 [pin AD16] - P0.21 [pin D2] - P0.22 [pin AD18] - P0.23 [pin AC19] - P0.24 [pin AD20] - P0.25 [pin AC21] - P0.26 [pin G1] - P0.27 [pin H2] - P0.28/AIN4 [pin B11] - P0.29/AIN5 [pin A10] - P0.30/AIN6 [pin B9] - P0.31/AIN7 [pin A8] - P1.00/TRACEDATA0 [pin AD22] - P1.01 [pin Y23] - P1.02 [pin W24] - P1.03 [pin V23] - P1.04 [pin U24] - P1.05 [pin T23] - P1.06 [pin R24] - P1.07 [pin P23] - P1.08 [pin P2] - P1.09/TRACEDATA3 [pin R1] - P1.10 [pin A20] - P1.11 [pin B19] - P1.12 [pin B17] - P1.13 [pin A16] - P1.14 [pin B15] - P1.15 [pin A14] - SWDCLK [pin AA24] - SWDIO [pin AC24] - VBUS [pin AD2] - VDD [pin A22] - VDD [pin AD14] - VDD [pin AD23] - VDD [pin B1] - VDD [pin W1] - VDDH [pin Y2] - VSS [pin B7] - VSS_PA [pin F23] - XC1 [pin B24] - XC2 [pin A23] ### U2 — [XC6220B331MR](https://www.flux.ai/kicad-part-library/xc6220b331mr~l55.md) - Manufacturer Part Number: XC6220B331MR - DropoutHeadroomCheck: Required — verify VIN headroom at max USB-host current; confirm VOUT (3.3V) + regulator dropout margin remains within worst-case VBUS sag and cable/connector losses; verify regulator can supply peak BLE and USB inrush currents. Reference: XC6220B331MR datasheet. - Datasheet URL: https://www.torexsemi.com/file/xc6220/XC6220.pdf - InputTransientRequirement: Required — specify VBUS transient protection requirements for upstream review (TVS clamping voltage, power rating, low capacitance if possible). - Role: Power Conversion - Package or Case Code: SOT-23-5 - Role Details: 5V to 3.3V LDO regulator for BLE SoC power rail **Pins:** - CE [pin 3] - GND [pin 2] - NC [pin 4] - VIN [pin 1] - VOUT [pin 5] *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/rintoj/zoophagous-amaranth-electromagnetic-shrinking-machine~ad](https://www.flux.ai/rintoj/zoophagous-amaranth-electromagnetic-shrinking-machine~ad).* --- *Generated from [https://www.flux.ai/rintoj/zoophagous-amaranth-electromagnetic-shrinking-machine~ad](https://www.flux.ai/rintoj/zoophagous-amaranth-electromagnetic-shrinking-machine~ad)*