ESP32-S3 Board Design

flux

The recovery pass has settled. I’m reconciling its report with a fresh live DRC now, then I’ll either finish the remaining routes or isolate the exact geometry that is genuinely blocked.

flux

The first recovery proved the issue is upstream, not a dirty board: the surgical router is incorrectly choosing the GND plane, and GPIO18 is physically boxed in by adjacent copper. I’ve started a final local-layout recovery with authority to minimally adjust J3/U1 and reroute only the obstructing copper while preserving USB, RF, crystal, and power sections.
Thought for 4 mins 53 sec
Awaiting 1 background task
Received notification from "PCB Connectivity Recovery" that it finished — picking the work back up.

flux

The stale GPIO1 trace was removed, clearing its dangling-trace and copper-overlap violations. The last verified PCB state is 13 airwires—12 GPIO connections plus Trace 8494—with no other blocking DRC errors and one non-blocking J1 edge warning.
The final connectivity-recovery executor has completed, but I cannot inspect or reconcile its changes because no ACUs are currently available. Remaining work is to rerun live DRC, verify the executor’s routing and any local placement changes, then independently review USB, RF, crystal, power, and return-current paths.
Check remaining DRC
Review USB and RF
Inspect remaining airwires
Resolve J1 edge warning
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Files

Schematic

Layout

Preview

Firmware Getting Started
Toolchain
  • Install ESP-IDF for ESP32-S3.
  • Target: esp32s3.
  • Configure flash size for the ESP32-S3FN8 integrated 8 MB flash.
  • Use native USB Serial/JTAG for flashing and logging.
Programming Sequence
  1. Connect USB-C.
  2. Normal programming should enumerate through native USB Serial/JTAG.
  3. If recovery is needed, hold BOOT (GPIO0 low), pulse RESET, then release BOOT.
  4. Flash with idf.py -p flash monitor.
Pin Map

Table

Board signalESP32-S3 pinNotes
USB_D−GPIO19Native USB Serial/JTAG; do not repurpose
USB_D+GPIO20Native USB Serial/JTAG; do not repurpose
BOOTGPIO0Strap; low during reset enters download mode
RESETCHIP_PUActive low hardware enable/reset
J3 GPIO1GPIO1General GPIO / ADC
J3 GPIO2GPIO2General GPIO / ADC
J3 GPIO4–14GPIO4–14General GPIO; ADC/touch functions vary by pin
J3 GPIO15XTAL_32K_P / GPIO15Available only because no 32 kHz crystal is fitted
J3 GPIO16XTAL_32K_N / GPIO16Available only because no 32 kHz crystal is fitted
J3 GPIO17GPIO17General GPIO
J3 GPIO18GPIO18General GPIO
J3 GPIO21GPIO21General GPIO
Minimal ESP-IDF Configuration
  • Enable USB Serial/JTAG console.
  • Keep GPIO19/20 assigned to USB.
  • Do not drive strapping pins externally during reset.
  • Treat GPIO15/16 as ordinary GPIO only while the external 32 kHz oscillator remains unused.
Example GPIO Bring-Up
C
#include "driver/gpio.h"

void app_main(void) {
    gpio_config_t io = {
        .pin_bit_mask = 1ULL << 4,
        .mode = GPIO_MODE_OUTPUT,
        .pull_up_en = 0,
        .pull_down_en = 0,
        .intr_type = GPIO_INTR_DISABLE,
    };
    gpio_config(&io);
    gpio_set_level(GPIO_NUM_4, 1);
}
Startup Order
  1. ROM boot and strap sampling.
  2. Clock and flash initialization.
  3. USB Serial/JTAG console.
  4. Configure only the GPIOs required by the application.
  5. Initialize Wi-Fi/Bluetooth after power and clock are stable.
Cautions
  • GPIO0 is not a general-purpose breakout pin in this design.
  • GPIO19/20 are reserved for USB.
  • GPIO15/16 cannot be used if a future revision adds a 32.768 kHz crystal.
  • RF calibration data and regulatory settings must match the final antenna and enclosure.

  • Toolchain

  • Programming Sequence

  • Pin Map

  • Minimal ESP-IDF Configuration

  • Example GPIO Bring-Up

  • Startup Order

  • Cautions