ESP32-S3 Board Design

Thought

The recovery pass has settled. I’m reconciling its report with a fresh live DRC now, then I’ll either finish the remaining routes or isolate the exact geometry that is genuinely blocked.

Worked

flux

The first recovery proved the issue is upstream, not a dirty board: the surgical router is incorrectly choosing the GND plane, and GPIO18 is physically boxed in by adjacent copper. I’ve started a final local-layout recovery with authority to minimally adjust J3/U1 and reroute only the obstructing copper while preserving USB, RF, crystal, and power sections.

Thought for 4 mins 53 sec

Awaiting 1 background task

Received notification from "PCB Connectivity Recovery" that it finished — picking the work back up.

Thought

flux

The stale GPIO1 trace was removed, clearing its dangling-trace and copper-overlap violations. The last verified PCB state is 13 airwires—12 GPIO connections plus Trace 8494—with no other blocking DRC errors and one non-blocking J1 edge warning.

The final connectivity-recovery executor has completed, but I cannot inspect or reconcile its changes because no ACUs are currently available. Remaining work is to rerun live DRC, verify the executor’s routing and any local placement changes, then independently review USB, RF, crystal, power, and return-current paths.

Check remaining DRC

Review USB and RF

Inspect remaining airwires

Resolve J1 edge warning

Files

Schematic

Layout

Preview

Design Notes

Verification Sources

Design values and topology were checked against the current ESP32-S3 Series Datasheet v2.2, ESP32-S3 Hardware Design Guidelines v1.8, Espressif reference schematics, and each active IC/connector datasheet. The datasheet extraction service returned OCR evidence without resolvable inline citation IDs, so claims are recorded as verified against named official documents but cannot carry Flux inline citations in this file.

Selected Parts

Table

Function	Part
MCU	ESP32-S3FN8
Buck regulator	TLV62568DBVR
USB-C	USB4105-GF-A
USB ESD	USBLC6-2SC6
VBUS PPTC	0805L110WR, 1.1 A hold
Crystal	CX2016DB40000D0FLJCC, 40 MHz, 8 pF, ±10 ppm
RF connector	U.FL-R-SMT-1(10)
Reset/boot switches	PTS810SJK250SMTRLFS
Breakout	1×20 1.27 mm THT socket footprint, M50-3032042 metadata

Regulator Design

Input: protected USB 5 V.
Output equation: VOUT = 0.6 × (1 + 453 kΩ / 100 kΩ) = 3.318 V.
Power stage: 4.7 µF input, 2.2 µH inductor rated 1.8 A, 10 µF output, 6.8 pF feed-forward.
1 A rating gives substantial margin over the 340 mA Wi-Fi TX peak and Espressif's ≥500 mA source recommendation.
Estimated USB input at 500 mA output, 90% efficiency: 367 mA.
LDO rejection: at 340 mA, (5 − 3.3) × 0.34 = 0.578 W, excessive for a compact narrow-board package without large thermal copper.

ESP32 Power Domains

VDD3P3 pins 2/3: filtered 3V3_RF rail through 2.1 nH / 600 mA inductor, with 10 µF, 1 µF, and two 100 nF capacitors.
VDDA pins 55/56: 3V3 with 1 µF + 10 nF.
VDD3P3_RTC: 100 nF.
VDD3P3_CPU: 100 nF.
VDD_SPI: tied to 3V3 for the FN8 3.3 V in-package flash, with 1 µF + 100 nF.
Exposed pad: ground.

USB

GPIO19 = D−, GPIO20 = D+.
0 Ω series links installed per Espressif guidance.
DNP 0402 shunt capacitor footprints are reserved at the SoC side.
CC1/CC2 each have 5.1 kΩ Rd.
USB D+/D− nets are tagged as a 90 Ω differential pair for the layout phase.

Crystal

40 MHz is mandatory for ESP32-S3 firmware.
Initial load capacitors are 12 pF C0G for an 8 pF-load crystal, assuming approximately 2 pF total stray contribution in the load equation.
A 24 nH series inductor is installed on XTAL_P as the Espressif initial harmonic-suppression value.
Frequency offset must be measured and load capacitors adjusted during RF qualification.

50 Ω path: LNA_IN → 1.5 pF shunt → 2.7 nH series → 1.5 pF shunt → u.FL.
These are initial values within Espressif's recommended tuning ranges, not guaranteed final production values.
Final four-layer PCB requires VNA/RF tuning, a continuous reference plane, short via-free RF routing, and layout-specific harmonic validation.

GPIO Breakout

18 safe exposed GPIOs: 1, 2, 4–18, 21. GPIO15/16 occupy the XTAL_32K pins and are usable because no 32.768 kHz crystal is fitted.

Validation Evidence

Schematic: 43 components, 40 nets.
Functional groups: USB/Protection, Regulator/Power, MCU/Crystal/RF, Reset/Boot, GPIO Breakout.
Review sweep included floating pins, no-connects, pin conflicts, shorts, missing power, single-pin/undriven nets, decoupling, pull resistors, capacitor voltage, part availability, footprints, and MPNs.
Final result: no unresolved OPEN, WARNING, ERROR, or UNCERTAIN findings in the requested electrical/passive/manufacturing review set.

Remaining Cautions

RF match and crystal load values require assembled-board tuning.
USB-C current advertisement is not measured; firmware/product use should remain within standard USB current expectations.
Flux did not expose a schematic-arrangement mutation tool in this run. Components are grouped by Functional Group and electrically complete, but a visual schematic-placement cleanup may still be desirable before handoff.

Verification Sources
Selected Parts
Regulator Design
ESP32 Power Domains
USB
Crystal
RF
GPIO Breakout
Validation Evidence
Remaining Cautions