Bloqueo Fuente 12V
Worked for 9 mins 58 sec
Me quedé bloqueado porque la cuenta ya no tiene ACUs disponibles, así que no puedo seguir ejecutando cambios ni crear el archivo de decisión.
Hecho hasta ahora
- Inspeccioné el proyecto: había 11 testpoints Keystone 5018 agregados.
- Detecté que esos 5018 causaban 11 errores DRC de cobre solapado por un pad mecánico duplicado.
- Reemplacé los 11 testpoints por
Generic Testpointde un solo pad y los reconecté a sus redes originales: GND, 3V3, 5V_SYS, USB D±, ESP_EN, ESP_BOOT, ADC_AC_VOLTAGE, ADC_CURRENT, RELAY_SET_GPIO y RELAY_RESET_GPIO. - Confirmé que IRM-45-12 y RACM40-12SK/OF/PCB-T no están como partes exactas en la librería, y no agregué un módulo 12 V/3 A falso.
Bloqueos / riesgos abiertos
- El proyecto todavía contiene cambios parciales inseguros del intento anterior:
U2 = IRM-30-12de 12 V/2.5 A,F2 = 2 A,J7,U6,C15–C17. Eso no cumple el requisito de salida auxiliar 12 V/3 A. - No pude revertir ni limpiar ese bloque parcial por falta de ACUs.
- No pude crear/actualizar el archivo
power-12v-production-decision. - Quedan DRC de airwires/routing; los errores de overlap de los testpoints quedaron abordados, pero falta verificación final completa.
Siguiente cuando haya ACUs
- Revertir/eliminar el bloque parcial 12 V subdimensionado (
IRM-30-12,F2 2A,J7,U6,C15–C17) o reemplazarlo solo con un módulo real 40–45 W con footprint confiable. - Restaurar la fuente original 5 V si corresponde o rediseñar la arquitectura con IRM-45-12/RACM40 real.
- Crear
power-12v-production-decisiondocumentando que ZMPT101B se mantiene y que 12 V/3 A queda bloqueado hasta disponer de parte/footprint certificado. - Ejecutar ERC/DRC final y corregir airwires/placement pendientes.
Documentar bloqueo
Buscar alternativas 12V
Revisar DRC/ERC
Eliminar bloque parcial
Refine this doc
Ask about this doc
Board Bring-Up Plan — ESP32-S3 IoT Relay Controller
Prerequisites
- Current-limited DC supply, isolation transformer/variac for AC tests, multimeter, oscilloscope, USB-C cable, insulated probes.
- Treat all AC-side nets as hazardous: AC_L_IN, AC_L_FUSED, AC_N, RELAY_COM_L, LOAD_L_SW.
- First power-up should use DC input only; do not connect mains until low-voltage rails and USB programming pass.
1. Visual Inspection
- Verify orientation of U2, U3, U5, U6, U7, Q1/Q2, LEDs, D5/D6/D7 and terminal blocks.
- Confirm creepage/clearance between mains and SELV zones before applying AC.
- Confirm fuse fitted in F1 only with a value appropriate to the target load and inrush.
2. Power Rail Verification
Table
| Rail | Source | Expected | Measure At | Current Limit | Pass Criteria |
|---|---|---|---|---|---|
| DC_IN_RAW | J4 | 5 V | J4 pin 1 to GND | 300 mA initial | No short / no overheating |
| DC_5V_PROT | F2 output | ~5 V | U7 VIN | 300 mA | TVS not conducting during normal input |
| 5V_SYS | U6/U7 outputs | 4.8–5.2 V | C10 | 300 mA initial | Stable before enabling relay |
| 3V3 | U3 output | 3.267–3.333 V nominal | C2/C3/U1 3V3 | 300 mA | ESP32 boots, no brownout |
| ACDC_5V | U2 output | 5 V | U6 VIN | AC test only | Isolated output, no SELV-to-mains continuity |
3. Critical Signal Verification
Table
| Signal | Expected Idle |
|---|---|
| ESP_EN | High after RC delay |
| ESP_BOOT / GPIO0 | High; BOOT button pulls low |
| ESP_STRAP_IO45 | Low |
| ESP_STRAP_IO46 | Low |
| RELAY_SET_GPIO / RELAY_RESET_GPIO | Low at boot |
| ACS_FAULT | High unless overcurrent threshold trips |
| I2C_SCL / I2C_SDA | Pulled high to 3V3 |
4. USB and Programming
- Power from DC input or verified 5V_SYS.
- Connect USB-C to J1.
- Confirm USB enumeration of ESP32-S3.
- Flash firmware from the Firmware Starter project file.
- Confirm serial output at 115200 baud.
5. Functional Validation
Table
| Test | Method | Pass Criteria |
|---|---|---|
| TMP102 | I2C read from 0x48 | Plausible board temperature |
| Relay set/reset | Pulse GPIO4/GPIO5 | Contact state changes; coils do not stay energized |
| Current ADC | Inject known load current | ADC estimate follows current after calibration |
| AC voltage ADC | Apply isolated/limited AC | Waveform centered around bias; RMS calibration possible |
| Protection | Trigger ACS fault where safe | Firmware resets relay |
6. AC Power Validation
- Perform only after visual inspection and DC bring-up pass.
- Use isolated test setup and current-limited AC source.
- Confirm U2 output isolation and 5V rail stability.
- Test relay with low-current lamp/load before 16 A thermal tests.
7. Production Tests
- Continuity of PE_PASS_THROUGH, AC_N, AC_L_IN, LOAD_L_SW.
- Hipot/isolation testing per target standard and certified component limits.
- Thermal run at rated load in enclosure.
- RF range test with final antenna.
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Critical Signal Verification
4. USB and Programming
5. Functional Validation
6. AC Power Validation
7. Production Tests
