# [2-layer] JLCPCB Constraints ## Description Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules ## Project Details - **Owner:** rambros - **Created:** 7/9/2025 - **Last Updated:** 7/9/2025 - **Visibility:** Public ## Key Components ### U1 — [AMS1117-3.3](https://www.flux.ai/jharwinbarrozo/ams1117-33~sbc.md) - Manufacturer Part Number: AMS1117-3.3 - Manufacturer Name: Kexin - Part Type: Integrated Circuit - Datasheet URL: https://www.lcsc.com/datasheet/lcsc_datasheet_2410122028_KEXIN-AMS1117-3-3_C369933.pdf **Pins:** - GND [pin 1] - TAB [pin 4] - VI [pin 3] - VO [pin 2] *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/rambros/2-layer-jlcpcb-constraints~v6](https://www.flux.ai/rambros/2-layer-jlcpcb-constraints~v6).* --- *Generated from [https://www.flux.ai/rambros/2-layer-jlcpcb-constraints~v6](https://www.flux.ai/rambros/2-layer-jlcpcb-constraints~v6)*