Product Development Lab Report Review
Thought for 37 sec
flux
Yes - here’s a placement keepout map you can use for the floorplan.
The reason to define these now is exactly to reduce the overlap and density risks before broader placement/routing, which matches the recommended
Recommended placement keepouts
inspect -> group -> ui-place -> place workflowTable
| Block | Keepout to use | What to keep out |
|---|---|---|
| U1 antenna end | 15 mm forward, 5 mm to each side | No copper, no pours, no traces, no vias, no components |
| U1 non-antenna body | 2 mm perimeter | Other component bodies |
| U2 TFT module body | 3 mm perimeter | Other component bodies |
| U2 header/fanout side | 8 mm routing corridor | Tall parts and blockages |
| LCD1 body | 3 mm perimeter | Other component bodies |
| LCD1 pin/header side | 6 mm routing corridor | Tall parts and dense copper escape obstacles |
| Each relay K1 to K4 body | 3 mm perimeter | Other component bodies |
| Each relay contact side | 5 mm separation from logic area | MCU/display low-voltage traces and parts |
| Between adjacent relays K1 to K4 | 2 mm minimum, 3 mm preferred | Neighboring relay bodies/copper crowding |
Use the strictest keepout here.
- In front of antenna edge: 15 mm
- Left/right of antenna zone: 5 mm
- Under antenna region: 0 copper on all layers
- Behind the rest of U1: normal 2 mm component keepout is fine
This is mostly a mechanical body + routing corridor keepout.
- Around module outline: 3 mm
- Along the signal/header edge: 8 mm
- Around any mounting holes or mechanical corners: 2 mm
- Do not place LCD1 inside this envelope
This part is bulky and usually blocks routing.
- Around body: 3 mm
- At the pin row / backpack side: 6 mm
- If it has mechanical standoffs or bezel overhang, reserve 2 mm extra around those features
Since you want to avoid a relay module, keep each relay as a discrete channel but give it real breathing room.
- Around each relay body: 3 mm
- Between neighboring relays: 2 mm minimum, 3 mm preferred
- From relay contact side to logic area: 5 mm
- Put driver parts like Q1 to Q4 and D8 to D11 inside the relay block, not in the MCU/display block
Use a stricter contact-side keepout:
Table
| Condition | Recommended contact-side keepout |
|---|---|
| Low-voltage DC loads only | 5 mm |
| Unknown load class | 6 mm |
| Mains switching | 6 mm minimum, more if your safety standard requires it |
- U1: center-left, antenna facing open board edge
- U2: top edge with 3 mm body keepout + 8 mm fanout corridor
- LCD1: top-right with 3 mm body keepout + 6 mm pin-side corridor
- K1 to K4: right side with 3 mm body keepout each and 5 mm isolation from logic region
Apply these as placement constraints first, then re-run overlap review. The layout workflow is designed for exactly this staged approach: inspect density/fit first, then group, then place UI/mechanical anchors before electrical placement
If you want, I can next convert this into a compact placement checklist with target X/Y regions for each block.
Use mains-safe spacing for every relay contact side and keep logic traces farther away.
Thought for 35 sec
flux
Understood - I would treat the relay contact side as mains-side copper from here forward.
Because the available project/report context does not establish a specific switched load voltage or safety standard, the safe approach is to treat that as an explicit design concern and use conservative spacing rather than assume a lower-voltage case . For layout work, that fits the staged placement-first workflow: define constraints early, then place blocks around them .
Updated mains-safe relay spacing rules
Contact-side spacing
Table
| Rule | Distance |
|---|---|
| Relay contact copper to any logic trace | 6 mm minimum |
| Relay contact copper to ESP32/display/I2C/SPI circuitry | 8 mm preferred |
| Relay contact copper to low-voltage component bodies | 6 mm minimum |
| Between adjacent switched-output nets if load class is uncertain | 3 mm minimum, 6 mm preferred |
| Keep logic traces out of relay/output edge corridor | 100% avoid |
Split each relay channel into two zones:
- Logic/coil side: Q1 to Q4, D8 to D11, base resistors, GPIO drive traces
- Contact/output side: relay COM/NO pads and the output connector side on U5 to U8
- No SPI, I2C, EN, BOOT, USB, or LED-control traces through the relay contact corridor.
- No logic traces between relay contact pins and the board edge connector area.
- Keep U1, U2, LCD1, and U4 fully outside that isolation band.
- Prefer the relay bank on one board side, logic on the opposite side, with a visible routing gap between them.
- 3 mm body keepout around the whole relay
- 6 mm minimum keepout on the contact/output side
- Q1 to Q4 and D8 to D11 stay on the coil side, not the contact side
- Align U5 to U8 so the switched copper path is short and direct
Use a simple separation policy:
- Left/center/top: logic and UI
- Right edge: relay bank
- Outer right or bottom-right edge: output connectors
- Isolation strip between logic and relay contacts: 6 mm minimum, 8 mm preferred
If the loads might ever be mains, I’d use:
- 8 mm preferred between relay contact copper and logic area
- 6 mm absolute minimum as the design floor
- no logic traces crossing that boundary at all
If you want, I can next convert this into a relay-side zone map with exact “logic boundary” and “contact boundary” labels for the floorplan.
Waiting for input
