PCB Design for Control System

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I ran out of execution credits during the placement-fix pass, so I stopped before placement adjustment, routing, or final DRC.
Completed so far:
  1. Battery keepouts added: YES — added 2 mechanical keepout zones:
    • BAT_CELL_A_32700_KEEP_OUT
    • BAT_CELL_B_32700_KEEP_OUT
  2. Fiducials added: YES — added 3 global fiducials:
    • FID1_GLOBAL
    • FID2_GLOBAL
    • FID3_GLOBAL
  3. Mounting holes added: YES — added 4 mounting holes:
    • MH1_MOUNT
    • MH2_MOUNT
    • MH3_MOUNT
    • MH4_MOUNT
  4. ESP32 antenna keepout added: YES — added ESP32_ANTENNA_KEEP_OUT
  5. GNSS keepout added: YES — added GNSS_ANTENNA_KEEP_OUT
  6. LoRa keepout added: YES — added LORA_ANTENNA_KEEP_OUT
  7. ELECTRODE_A_HV keepout added: YES — added ELECTRODE_A_HV_ISOLATION_KEEP_OUT
  8. Flex-tail support added: PARTIAL — added FLEX_TAIL_POTTING_STRAIN_RELIEF_KEEP_OUT, FLEX_PIN1_MARK, and two flex alignment marks.
  9. HV warning silkscreen added: YES — added HV_WARNING_TEXT
  10. Routed: NO
  11. Remaining unrouted nets count: not rechecked after the added keepouts; previously expected airwires remained because the board was not routed.
  12. Remaining DRC error count: not rechecked after the added keepouts.
Still needed before routing:
  • Run one placement adjustment pass to move components/test points out of the new battery, antenna, flex, and HV keepouts.
  • Verify mounting holes/fiducials have adequate clearance.
  • Verify flex-tail zones are physically separated.
  • Run DRC and confirm the only remaining DRC issues are airwires.
  • Only then proceed with routing if blockers are resolved.
Run DRC blockers
Fix placement conflicts
Verify flex zones
Check assembly clearances
Inspect RF paths
Sign up to send

Files

Schematic

Layout

Preview

Board Bring-Up Plan — CONTROL_RF_PCB
Prerequisites
  • Equipment: microscope, multimeter, current-limited bench supply or external power board, oscilloscope, USB-UART adapter, RF test equipment/VNA if available, known-good LoRa and GNSS antennas.
  • Firmware: use the companion firmware starter file after first power checks pass.
  • Safety: ELECTRODE_A_HV is an isolated pass-through from an external stimulation board. Do not connect HV during first low-voltage bring-up.
1. Visual Inspection
  • Confirm orientation and solder quality for U1 ESP32-S3, U2 SX1262, U3 MAX-M10S, U4 BMA400, U5 TMP117, MK1 microphone, U6 RF switch, ESD/TVS diodes, and MOSFETs.
  • Inspect U.FL connectors J_LORA_ANT and J_GNSS_ANT for center-pin shorts to ground.
  • Confirm microphone acoustic port is clear.
  • Confirm electrode silkscreen/keepout and flex-tail pad zones are physically separated.
2. Power Rail Verification

Table

RailSourceExpected VoltageMeasure AtInitial Current LimitPass Criteria
3V3External power board via flex tail3.0 to 3.6 V, nominal 3.3 VTP_3V3250 mA first power, then 800 mANo overheating; voltage in range
GNSS_3V3_FILT3V3 through FB_GNSSabout 3.3 VU3 VCC or C9Included in 3V3Within 100 mV of 3V3 at idle
CELL_PACK_PLUSLocal 1S LiFePO4 pack bus2.5 to 3.65 V typical LiFePO4 rangeTP_CELL_PACK_PLUSBattery source current-limited if possibleNo short to GND before battery connection
SOLAR_A_PLUS6 V nominal solar panel pass-through0 to panel open-circuit voltageTP_SOLAR_A_PLUS250 mANo short; does not backfeed 3V3
ELECTRODE_A_HVExternal stimulation board onlyDo not energize during low-voltage bring-upTP_ELECTRODE_A_HVN/AIsolated from 3V3, GND, RF, GNSS, I2C, SPI, UART
Procedure:
  1. With no power applied, measure resistance from 3V3 to GND, CELL_PACK_PLUS to GND, SOLAR_A_PLUS to GND, and ELECTRODE_A_HV to all low-voltage rails.
  2. Apply 3.3 V at the flex-tail 3V3/GND pads with a 250 mA current limit.
  3. Measure TP_3V3 and GNSS_3V3_FILT.
  4. Increase current limit only after confirming no excessive current draw or hot components.
3. Critical Signal Verification

Table

SignalExpected StateMeasure AtNotes
ESP_ENHigh, about 3.3 V after RC delayTP_ESP_ENRESET button should pull low
ESP_IO0High for normal bootTP_ESP_IO0BOOT button should pull low for bootloader
UART_TX/UART_RX3.3 V UART activity during boot/programmingTP_UART_TX, TP_UART_RXUse USB-UART at 3.3 V logic
LORA_SCK/MOSI/MISO/NSSSPI activity during LoRa initTest pointsSPI mode 0, up to 16 MHz per SX1262 datasheet
LORA_BUSYLow when SX1262 readyTP_LORA_BUSYFirmware must wait while high
LORA_DIO1Interrupt outputTP_LORA_DIO1Verify after LoRa driver init
GNSS_TX/GNSS_RX9600 baud default UARTTP_GNSS_TX, TP_GNSS_RXMAX-M10S default NMEA/UBX output
MIC_BCLK/MIC_WS/MIC_SDI2S clocks/dataMK1 pins or scope padsVerify after firmware starts I2S
4. Connector and Interface Tests

Table

Connector / Pad ZonePins / NetsTest Method
J_UART_DBGGND, UART_RX, UART_TX, 3V3Continuity and 3.3 V UART programming test
J_FLEX_TAIL_CONTROL_SIG20 low-voltage flex padsContinuity to each named net; verify pin 1 marker
J_FLEX_BATT_P / J_FLEX_BATT_GCELL_PACK_PLUS, GND/PACK_GNDHigh-current continuity and polarity check
J_FLEX_SOLAR_ASOLAR_A_PLUSContinuity to solar pass-through, no 3V3 short
J_ELECTRODE_AELECTRODE_A_HVIsolation resistance to all low-voltage nets
J_VIB_ACELL_PACK_PLUS, VIB_A_OUTLow-current motor test with current limit
J_BUZZ_ACELL_PACK_PLUS, BUZZ_A_OUTLow-current buzzer test with current limit
J_LORA_ANTLORA_ANTCheck no center-to-shield short; RF tune later
J_GNSS_ANTGNSS_ANTCheck no center-to-shield short
5. Programming and Debug Interface
  • Interface: UART0 using J_UART_DBG.
  • BOOT: hold SW_BOOT low, pulse SW_RESET/EN low, then release BOOT.
  • Tool: PlatformIO upload or esptool.py for ESP32-S3.
  • Pass criteria: boot ROM messages visible on UART_TX and firmware serial output at 115200 baud.
6. Functional Validation

Table

TestComponentsExpected Result
I2C scanU4 BMA400, U5 TMP117BMA400 at 0x14 and TMP117 at 0x48 respond
Temperature readTMP117Ambient reading plausible within a few degrees
IMU interrupt checkBMA400INT pins change after firmware configuration
GNSS UARTMAX-M10SNMEA/UBX output at default 9600 baud; fix after antenna view of sky
LoRa SPISX1262BUSY behavior and register/command responses valid
LoRa RFSX1262, U6, RF network, U.FLRequires RF test/tuning; confirm 915 MHz matching before compliance use
MicrophoneICS-43434I2S data changes with acoustic input
Vibration driverQ_VIB_A and J_VIB_AVIB_A_OUT switches low when PWM active
Buzzer driverQ_BUZZ_A and J_BUZZ_ABUZZ_A_OUT switches low when PWM active
Battery senseR12/R13 dividerADC-derived voltage matches TP_CELL_PACK_PLUS within divider tolerance
Solar senseR14/R15 dividerADC-derived voltage matches TP_SOLAR_A_PLUS within divider tolerance
HV isolationJ_ELECTRODE_ANo continuity to low-voltage or RF nets
7. Pass/Fail Summary

Table

SectionResultNotes
Visual Inspection[ ] Pass / [ ] Fail
Power Rails[ ] Pass / [ ] Fail
Programming[ ] Pass / [ ] Fail
Sensor Interfaces[ ] Pass / [ ] Fail
RF/GNSS[ ] Pass / [ ] Fail
Actuators[ ] Pass / [ ] Fail
Flex Tail / HV Isolation[ ] Pass / [ ] Fail
Board Status: [ ] Ready for environmental prototype testing / [ ] Requires rework

  • Prerequisites

  • 1. Visual Inspection

  • 2. Power Rail Verification

  • 3. Critical Signal Verification

  • 4. Connector and Interface Tests

  • 5. Programming and Debug Interface

  • 6. Functional Validation

  • 7. Pass/Fail Summary