This fork contains 36 components and 27 nets, not the three-component/zero-net checkpoint described in older project files. Read-only full schematic inspection found existing MCU supply and ground, four VDD bypass capacitors C1–C4, isolated VCAP capacitors C5/C6, bulk C7, VDDA/VBAT bypass C8/C9/C11, reset C10, boot straps R1/R2, oscillator Y1/C20, USB-C CC resistors R5/R6, ESD D2, USB diode D1, two LDOs U4/U5 and C16–C19, IMU SPI/power/interrupt connections and flash SPI/power/CS pull-up already wired. No missing connection in these support blocks was established that justifies changing the inherited netlist. No schematic or PCB entities were changed in this audit. This does not establish complete electrical or flight readiness.

NRST uses the permanent internal pull-up and existing 100nF capacitor C10; an extra external pull-up is not required merely to silence ERC. IMU reserved pin7 is grounded; pins2/3/10/11 may remain unconnected. Flash HOLD is held high for single-SPI operation, which avoids pausing while selected.

AP2112 pin5 is VOUT and pin3 EN is active high; both existing EN pins connect to the upstream USB_CORE_5V rail. The datasheet shows 1uF input/output capacitors and states stability with 1uF; it does not support describing that figure as an explicit minimum in C16–C19 role text. Effective capacitance, chosen dielectric, ratings, thermal behavior, reverse discharge and startup remain verification gates.

Authoritative public source read in full: Betaflight configuration, repository commit prefix 1e3f7782bfbc, retrieved 2026-10-07. The former path configs/SPEEDYBEEF405V5/config.h no longer resolves; the manufacturer subdirectory is required.

Inherited IMU and flash pin nets match these named reference signals. That is not complete target compatibility: gyro orientation/CLKIN timer implementation, flash JEDEC support, barometer, OSD, external interfaces, analog sensing/calibration and power controls are not implemented or verified. The active oscillator Y1 requires clock-source configuration appropriate to an external driven clock; the target's 8MHz frequency alone does not prove the existing binary supports that topology. OSC_IN is the external user-clock input. Exact bypass startup/OSC_OUT handling remains a firmware/reference-manual gate; do not replace the oscillator with a guessed crystal/load network.

Manufacturer product page confirms ten-pin rear connector but retrieved content does not supply a numbered contact map. Existing reference-review records eight solder functions M4/M3/M2/M1/TLM/current/GND/VBAT; these do not establish ten-contact numbering, duplicated contacts, orientation or mating connector. No harness connector, VBAT sense or current input was guessed. Required next evidence: authoritative numbered connector drawing and mating-view orientation, or verified continuity measurements on original hardware. Do not directly feed VBAT into an MCU/LDO input.

Same manufacturer page confirms FC39x39x4.9mm and 30.5x30.5mm mounting, diameter4mm side opening; ESC40.9x44.9x8mm explicitly includes heatsink. Keep two separate unequal-size boards. No dimensioned bare ESC outline, side-notch geometry or original absolute pad coordinates was obtained. Published envelope is not bare-PCB fabrication geometry; require manufacturer CAD or measured original board. No ESC project was accessed or edited.

Oxbot firmware page describes OX32 ESC firmware and supported protocols, not a custom-hardware integration contract. Oxbot FAQ says download/update methods will be announced and specific hardware compatibility depends on official updates. A web configurator endpoint is advertised publicly at https://ox32.oxbot.com/; existence of a configurator does not establish bootloader access, redistributable binaries, source licensing, exact MCU/pin mapping, or support for a new ESC PCB. These remain unverified. Do not promise OX32, proprietary SpeedyBee app support, or a validated55A capability for a recreated board.

Read-only ERC on 2026-10-07:44 errors,0 warnings:34 floating MCU pins,2 missing-power reports on U2 VDD/VDDIO,8 undriven USB connector power/ground pins. Missing-power reports are inconsistent with inspected 3V3_IMU membership including U5 VOUT; inspect part pin typing/source inference before adding dummy power flags or changing valid supply connectivity. USB source is external; eight connector reports do not justify adding an on-board VBUS source. Floating pins are future motor/UART/OSD/I2C/ADC/control interfaces, not presently unused pins to blanket-mark NC. These errors remain open, not cleared or waived. ERC does not validate startup, supply levels, clock firmware or current ratings.