Project Start

Thought for 7 mins 25 sec

Awaiting 1 background task

Received notification from "PRG32 Console Revision" that it finished — picking the work back up.

Thought for 45 sec

flux

The two-sided placement, 3D preview, and full reroute are complete and clean. One electrical limitation remains: both SETUP buttons are correctly paralleled, but GPIO14 is not exposed on the selected socketed DevKit headers, so the SETUP net cannot reach the ESP32 without a physical bodge/test-point wire or a different DevKit carrier.

Worked for 26 sec

flux

Revised both sides and updated the 3D placement:

Front: centered landscape TFT, joystick with MID on the left, horizontally aligned A/B on the right, and two centered SETUP buttons above/below the display.
Rear: centered USB-accessible DevKit, mirrored MAX98357A modules and audio passives, symmetric speakers, and preserved JST speaker polarity.
Board remains 180 × 100 mm, 4 layers. Routing and DRC are clean: 0 airwires, 0 dangling traces, overlaps, bounds, or keepout violations.

Open item

The two SETUP buttons are paralleled to GND on BTN_SETUP_GPIO14, but the socketed ESP32-C6 DevKit does not expose GPIO14 on its headers. The SETUP net therefore cannot reach the MCU through the existing sockets.

Next steps

Add a documented bodge/test-point connection from the DevKit’s GPIO14 pad to the PCB.
Alternatively assign SETUP to an exposed GPIO, such as GPIO15.
Use another ESP32-C6 carrier that exposes GPIO14.

Expose GPIO14 safely

Use GPIO15 setup

Select alternate carrier

Prepare manufacturing review

Files

Schematic

Layout

3D View

Firmware Getting Started

Use ESP-IDF v5.4 with ESP32-C6 support or the repository's prg32-esp32c6 PlatformIO environment. The hardware target is the socketed Waveshare ESP32-C6-DEV-KIT-N8; it is programmed and powered through its retained USB-C connector.

Carrier pin map

Table

Peripheral	GPIO
TFT SPI	MOSI 7, MISO 2, SCLK 6, CS 10, D/C 1, reset 0, backlight 5
Optional resistive touch SPI	shared MOSI 7, MISO 2, SCLK 6; CS 12; IRQ not connected
Controls	UP 3, DOWN 13, LEFT 18, RIGHT 19, START/SELECT 20, A 21, B 22
Stereo I2S	BCLK 4, LRCLK 11, DIN 23
Reset	development-board EN/CHIP_PU; not a gameplay GPIO
RGB LED	GPIO8 is disabled; no carrier circuit

The confirmed J5 display socket is a 1×14 2.54 mm female socket for the B082QVKT7M-compatible ILI9341 interface. Its fixed order is VCC, GND, CS, RESET, DC, MOSI, SCK, LED, MISO, T_CLK, T_CS, T_DIN, T_DO, T_IRQ. VCC is 3.3 V. The documented compatible module does not identify the touch-controller IC, so do not select an XPT2046 driver merely from the header labels; inspect the module marking or obtain its vendor documentation first.

Configure all gameplay GPIOs as inputs with internal pull-ups and treat pressed as low. Configure GPIO4/11/23 as the shared I2S TX bus; U2 is wired for left and U3 for right. For the display, configure GPIO5 as a high-active backlight enable/PWM output. If touch support is verified, initialize the TFT with CS high before selecting GPIO12 for a touch transaction; J5 T_IRQ is intentionally unavailable.

Build commands

Bash
idf.py -B build-esp32c6 -D SDKCONFIG=build-esp32c6/sdkconfig -D SDKCONFIG_DEFAULTS=sdkconfig.defaults set-target esp32c6
idf.py -B build-esp32c6 -D SDKCONFIG=build-esp32c6/sdkconfig -D SDKCONFIG_DEFAULTS=sdkconfig.defaults build
idf.py -B build-esp32c6 -D SDKCONFIG=build-esp32c6/sdkconfig -D SDKCONFIG_DEFAULTS=sdkconfig.defaults flash monitor

Carrier pin map
Build commands