• Production-intent power module for SAI equipment.
• Powered only from a regulated 5 V source.
• Supports combined load currents requiring verification of 12 A continuous-current capability through the entry stage.
• Uses a dry external contact as the RUN command.
• Separates logic-return and motor-return currents through a controlled single-point star-ground architecture.

• Accept regulated 5 V through a redundant-contact input connector.
• Protect against reverse polarity with a P-channel MOSFET stage.
• Disconnect power when the RUN dry contact is open.
• Enter the RUN state when the RUN contact closes to input ground.
• Fail safely OFF if the RUN wiring or contact opens.
• Distribute switched power independently to protected logic and motor rails.
• Keep logic and motor grounds domain-local except for their dedicated star bonds.
• Provide color-coded power indicators and accessible test points.

• Reverse-polarity and fail-safe series power switching.
• External dry-contact-only RUN control.
• Independent resettable protection for logic and motor outputs.
• Large low-ESR bulk capacitance on both output domains.
• Dedicated logic and motor diagnostic LEDs.
• Red positive-rail and black ground test points.
• Non-negotiable single-point ground-star implementation.

Diagram

Text
VIN_5V (SAI_5V_SUPPLY) + RUN_SW_GATE (external dry contact)
        ↓
   PWR_ENTRY
        ↓
   ┌────┴────┐
   ↓         ↓
LOGIC_DIST  MOTOR_DIST
   ↓         ↓
LOGIC_5V   MOTOR_V

• ENT_J1: 2EDGVC-5.08-4P.
  • Pins 1 and 3: VIN_5V.
  • Pins 2 and 4: GND_IN.
• ENT_J2: XD2EDGVC-5.08-2P.
  • Pin 1: RUN_SW_GATE.
  • Pin 2: GND_IN.
  • Close pin 1 to pin 2 to command RUN.
  • Open contact commands fail-safe OFF.
  • Dry contact only; no external voltage may be applied.

• Back-to-back P-channel MOSFETs using AON6403-VB:
  • ENT_Q1: reverse-polarity stage; gate tied to GND_IN.
  • ENT_Q2: series fail-safe KILL stage.
• All source and drain pins intended to operate in parallel must receive broad copper and dense via support.

• ENT_R1: 100 kΩ, 1%.
• ENT_R2: 1 kΩ, 1%.
• ENT_C1: 10 nF, 25 V, X7R.
• Preserve the hardware value ENT_R1 × ENT_C1 = 1 ms.
• Gate-line TVS: SMAJ18CA-E3/61.

ENGINEERING WARNING — GATE TIMING: Including the specified MOSFET input capacitance does not support any 10 µs / 1.9 ms turn-off claim. Actual turn-on and turn-off times must be measured on the bench before release.

ENGINEERING WARNING — VGS PROTECTION: The specified TVS has a 29.2 V rated clamp, exceeding the AON6403-VB ±20 V VGS absolute maximum. The TVS does not guarantee VGS protection for arbitrary overvoltage. A regulated 5 V VIN is mandatory; the TVS is supplementary only.

• 10 µF, 25 V, X7R.
• 100 nF, 25 V, X7R.

• ENT_R3: 0 Ω; the only bond from GND_IN to LOGIC_GND.
• ENT_R4: 0 Ω; the only bond from GND_IN to MOTOR_GND.
• Route each bond as its own independent branch from the star point.
• No other copper, shield, mounting feature, connector, test feature, or mechanical path may electrically connect the domains.

• ENT_TP1: GND_IN, black.
• ENT_TP2: LOGIC_GND, black.
• ENT_TP3: MOTOR_GND, black.

• Input: PWR_5V.
• LOG_F1: BSMD2920-400-16V resettable fuse.
  • Hold current: 4 A.
  • Trip current: 8 A.
• Protected output rail: LOGIC_5V.

• LOG_C1: at least 2200 µF, 16 V, low-ESR, 105 °C radial THT electrolytic.
  • Required footprint: diameter 12.5 mm, 5.00 mm pin pitch.
  • Pin 1 must be positive.
  • Any Circuit JSON package field is a schema placeholder only and must not replace the real radial THT footprint.
• LOG_C2: 100 nF, 16 V, X7R.

• LOG_J1: 2EDGVC-5.08-4P.
  • Pins 1 and 3: LOGIC_5V.
  • Pins 2 and 4: LOGIC_GND.
• LOG_D1: KT-0603G green LED.
• LOG_R1: 470 Ω, 1%.
• LOG_TP1: RH-5000 red test point on LOGIC_5V.
• LOG_TP2: RH-5001 black test point on LOGIC_GND.

• LOGIC_GND is domain-local.
• ENT_R3 is the only allowed bond between LOGIC_GND and GND_IN.

• Input: PWR_5V.
• MOT_F1: ESMD1812L-800-12V or procurement-approved BSMD equivalent.
  • Hold current: 8 A at 25 °C.
  • Trip current: 16 A at 25 °C.
  • Apply ambient-temperature hold-current derating.
  • Validate the motor startup-current pulse against the fuse time-current behavior.
  • Any BSMD ↔ ESMD substitution requires procurement approval before release.
• Protected output rail: MOTOR_V.

• MOT_C1: at least 4700 µF, 16 V, low-ESR, 105 °C radial THT electrolytic.
  • Must use an approved real radial footprint.
  • Any Circuit JSON package field is a schema placeholder only.
• MOT_C2: 100 nF, 16 V, X7R.
• MOT_C3: 10 µF, 16 V, X7R.

• MOT_J1: 2EDGVC-5.08-4P.
• MOT_D1: HSMA-C170-T0000 amber LED.
• MOT_R1: 680 Ω, 1%.
• MOT_TP1: RH-5000 red test point on MOTOR_V.
• MOT_TP2: RH-5001 black test point on MOTOR_GND.

• MOTOR_GND is domain-local.
• ENT_R4 is the only allowed bond between MOTOR_GND and GND_IN.

• Input voltage: regulated 5 V mandatory.
• No battery, charging, or runtime requirement is defined.
• Entry-stage copper and MOSFET interconnect must be verified for 12 A continuous operation.
• Logic branch protection target: 4 A hold / 8 A trip.
• Motor branch protection target: 8 A hold / 16 A trip at 25 °C, with ambient derating and startup-pulse validation.

• Production-ready hierarchical schematic with sheets named exactly:
  • PWR_ENTRY
  • LOGIC_DIST
  • MOTOR_DIST
• Preserve all specified designators and net names.
• Complete BOM must include:
  • Manufacturer part numbers.
  • Confirmed fuse hold and trip currents.
  • Real radial THT footprints for bulk capacitors.
  • LED colors.
  • Approved substitutions and procurement status.
• No thermal relief on high-current MOSFET, fuse, capacitor, or connector current-carrying pins where prohibited by the layout requirements.
• Use broad power copper and dense vias.
• Do not double connector current ratings without connector-manufacturer approval.
• Missing exact library parts must not be silently replaced with differently rated or differently colored variants.

• None. RUN control is a hardware dry-contact input and must not depend on firmware for fail-safe shutdown.

• Broad copper on every parallel MOSFET source and drain pin.
• Dense vias around the MOSFET current path.
• Verify 12 A continuous-current capability thermally and electrically.
• Wide MOTOR_V and MOTOR_GND pours.
• Multiple vias at MOT_F1, motor capacitors, and both contacts of each output polarity.
• Ground domains must remain physically and electrically separate except at ENT_R3 and ENT_R4.
• Test points and connectors must remain accessible for production test and bench validation.

1. Regulated 5 V input is mandatory.
2. RUN input is dry-contact only; no external voltage may be applied.
3. Open RUN contact means fail-safe OFF.
4. Actual gate turn-on and turn-off timing must be measured before release; the specified network and Ciss do not support a claimed 10 µs / 1.9 ms turn-off timing.
5. The SMAJ18CA-E3/61 29.2 V clamp exceeds the MOSFET ±20 V VGS absolute maximum and is only supplementary protection.
6. ENT_R3 and ENT_R4 are the only permitted ground-domain bonds.
7. No shield, mounting, connector, copper, or mechanical ground path may bypass the star bonds.
8. Motor fuse hold current requires ambient derating and startup-pulse validation.
9. Any BSMD ↔ ESMD motor-fuse substitution requires procurement approval.
10. Parallel connector contacts do not automatically double rated current.

• Hierarchical sheets and all required designators/net names exactly match this specification.
• ENT_J1 pins 1/3 connect only to VIN_5V; pins 2/4 connect only to GND_IN.
• ENT_J2 implements dry-contact RUN exactly as specified and has no path intended for an externally driven voltage.
• ENT_Q1 polarity and gate connection provide reverse-polarity protection.
• ENT_Q2 opens on loss of the RUN contact and provides fail-safe OFF behavior.
• ENT_R3 is the sole GND_IN–LOGIC_GND bond.
• ENT_R4 is the sole GND_IN–MOTOR_GND bond.
• No unintended second ground path exists through copper, shields, mounting hardware, connectors, test points, or mechanical features.
• All mandatory warnings appear on the schematic sheets.

• Exact MPNs and lifecycle status are verified for production.
• Symbols, pin mappings, and footprints are checked against authoritative datasheets.
• LOG_F1 is confirmed at 4 A hold / 8 A trip.
• MOT_F1 is confirmed at 8 A hold / 16 A trip at 25 °C.
• Motor-fuse temperature derating and startup-pulse compatibility are documented.
• Any motor-fuse substitution has written procurement approval.
• LOG_C1 uses a real D12.5 mm / P5.00 mm radial THT footprint with pin 1 positive.
• MOT_C1 uses an approved real radial THT footprint with correct polarity and dimensions.
• LED MPNs and colors are verified: LOG_D1 green and MOT_D1 amber.
• Test-point MPNs and colors are verified.
• Connector current ratings are validated without assuming parallel contacts double current capability.

• Confirm correct operation at regulated 5 V input across allowed input tolerance.
• Confirm reverse-polarity input does not energize PWR_5V, LOGIC_5V, or MOTOR_V and causes no component overstress.
• Confirm closed RUN contact enables the module.
• Confirm open, disconnected, or broken RUN contact causes fail-safe OFF.
• Measure ENT_Q2 gate, PWR_5V, and load voltage during turn-on and turn-off under representative loads.
• Record actual turn-on and turn-off timing; do not release using an unmeasured 10 µs / 1.9 ms claim.
• Measure peak VGS during normal switching and expected transients; verify it remains within ±20 V.
• Verify logic and motor indicator operation and color.
• Verify all test-point voltages and domain identities.
• Validate motor startup current against MOT_F1 nuisance-trip and protection behavior.

• Review current density on all parallel MOSFET source/drain pins.
• Verify broad copper, dense vias, and absence of prohibited thermal reliefs.
• Demonstrate 12 A continuous operation at worst-case ambient and representative enclosure airflow.
• Measure MOSFET, fuse, connector, capacitor-terminal, via-field, and PCB copper temperatures to defined acceptance limits.
• Verify voltage drop from ENT_J1 to both output connectors at rated load.
• Confirm motor pours and via arrays meet the required current and temperature-rise targets.
• Inspect ground geometry to prove independent star branches and no shared return segment that compromises domain isolation.

• Gate timing has been measured and documented.
• VGS behavior has been measured and shown safe for the MOSFET.
• 12 A continuous-current thermal validation has passed.
• Motor startup-pulse and ambient fuse derating have passed.
• Connector current capability is approved.
• Exact production footprints and polarities are confirmed.
• Ground-domain isolation and sole-bond rules are verified by schematic review, layout review, and continuity testing.
• All substitutions have engineering and procurement approval.
• Complete BOM, fabrication data, assembly data, and validation records are approved.

• Use P-channel MOSFET high-side switching for reverse-polarity and fail-safe control.
• Keep hardware fail-safe behavior independent of software.
• Split protected power into logic and motor domains after the entry stage.
• Implement domain returns using two dedicated 0 Ω star branches.
• Treat the gate TVS as supplementary protection only.
• Require real measured switching timing and thermal performance before production release.

• VIN_5V is externally regulated and never intentionally exceeds the input requirements of the specified components.
• Exact mechanical dimensions and mating compatibility will be checked against authoritative connector datasheets before layout approval.
• Final motor connector pin assignment will be explicitly documented on the schematic.
• Acceptance temperature-rise limits will be defined before formal thermal testing.
• Parts missing from the current library will be sourced, imported, or created only from verified manufacturer data; incorrect electrical or color variants are not acceptable substitutes.

• Initial specification generated from the final-release power-module prompt.
• All stated production warnings, domain-isolation rules, footprints, component values, and release validation requirements have been retained.