High-Voltage Amplifier Specification Review
Thought for 12 sec
已按这个约束处理，并已写入项目规格：
- 外部接口仅保留三类：220VAC 供电口、信号输入口、信号输出口
- 不允许外部 ±HV 电源、外部控制、外部反馈、外部使能、外部调试或辅助电源接口
- 电源架构固定为：220VAC 输入 → 内部保护/EMI/浪涌/整流/PFC → 内部隔离 HV/LV 电源 → BTL 高压输出级
- 所有保护、监测、放电、互锁、限流、反馈都必须做在设备内部
下一步原理图就按这个边界开始，不再考虑外部高压电源方案。
为信号输入和输出添加隔离接口
Thought for 21 sec
我会把信号输入/输出隔离纳入架构：先检查空原理图和现有项目文件，再选择可满足 DC–500 kHz 的隔离实现边界，最后更新规格并在原理图中加入接口占位/隔离功能块。
Worked for 16 mins 58 sec
研发完整的电路图
研发完整的电路图
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Project Specification - HV Arbitrary Waveform Amplifier
Design Summary
Status: Draft / architecture definition
Manufacturing target: Prototype / engineering validation
Purpose: Design a high-voltage arbitrary waveform amplifier powered only from 220 VAC mains, accepting a low-voltage arbitrary waveform input and driving a capacitive high-voltage output load with controlled slew rate and hardware protection.
Scope
In scope
- Exactly three external interaction/interface categories:
- 220 VAC voltage power supply interface
- Signal input interface
- Signal output interface
- Internal 220 VAC input protection, EMI filtering, inrush limiting, rectification/PFC as required, isolated HV and LV power conversion
- Internal signal conditioning and control/modulation
- Internal high-voltage output stage
- Internal HV voltage feedback and current sensing
- Internal overcurrent, overvoltage, overtemperature, arc/short, discharge, and interlock protection
- Domestic / China supply-chain component preference where technically safe
Out of scope for first schematic freeze
- PCB layout and routing before schematic review
- Manufacturing release before safety, thermal, EMI, and SOA validation
- External debug, enable, feedback, fault, auxiliary power, external HV rail, or external control connectors
System context
The project is a self-contained HV arbitrary waveform amplifier. The outside world connects only to 220 VAC power input, signal input, and HV signal output. All monitoring, protection, auxiliary power, discharge, interlock, and control functions are internal to the unit.
Requirements
Functional
- Accept fixed 220 VAC mains input through the power interface.
- Accept ±10 V arbitrary waveform signal input.
- Produce up to ±1000 V peak arbitrary waveform output.
- Drive a 1.5 nF capacitive load.
- Operate over a tentative 0 to 500 kHz bandwidth target.
- Treat full-scale 500 kHz operation as burst operation for the first design; initial full-scale burst duration target is 10 ms.
- Enforce 6 A peak overcurrent protection.
- Enforce output slew-rate limiting to ≤4000 V/µs.
- Expose only three interface categories externally: power input, signal input, signal output.
- Prefer domestic / China supply-chain components where safety and performance allow.
Electrical
- AC input: fixed 220 VAC mains.
- Closed-loop voltage gain target: 100 V/V.
- Full-scale 500 kHz sine into 1.5 nF requires approximately 4.71 A peak.
- 6 A into 1.5 nF corresponds to 4000 V/µs maximum slew rate.
- Output capacitive energy from 0 to 1000 V is about 0.75 mJ.
- Full-scale sine reactive apparent power is approximately 2.36 kVA.
- 10 ms at 500 kHz equals 5000 full-scale cycles; local HV storage, dump/absorption, output devices, and thermal design must tolerate this burst.
- Conservative early HV storage placeholder: design around about 25 J burst energy envelope for 1.5 nF at full-scale 500 kHz, then refine after output-stage topology and recovery method are selected.
- First architecture direction: floating differential BTL fixed-HV-rail linear amplifier with internal mains-derived isolated supplies.
- Suggested internal HV rails per leg: ±600 V to ±650 V.
- Low-voltage internal rails expected: ±15 V analog, 5 V, 3.3 V, plus isolated driver rails as required.
Key constraints
- 220 VAC mains input requires fuse, MOV/surge protection, EMI filtering, inrush limiting, protective earth strategy, isolation, creepage/clearance, and discharge design.
- High voltage creepage, clearance, insulation slots, enclosure safety, and discharge paths are mandatory.
- HV output must include a safe connector and cable strategy, not ordinary low-voltage connectors.
- Output current limiting must be analog/hardware enforced; firmware-only protection is insufficient.
- Fixed-rail linear BTL is acceptable for first control/output-stage validation under 10 ms full-scale burst operation, but high duty-cycle or continuous full-scale 500 kHz operation may require tracking rails, multilevel switching, or energy recovery.
- Safety-critical parts may use international/certified brands if domestic parts lack adequate certification, datasheet clarity, voltage rating, or reliability.
- No external ±HV supply interface is allowed.
Dependencies and risks
Dependencies
- Confirm whether output may be floating differential or must be ground-referenced.
- Confirm repetition rate / cooldown interval for the 10 ms full-scale burst.
- Confirm cooling method and enclosure constraints.
- Confirm applicable safety standard target.
- Select or design internal 220 VAC to isolated HV/LV power architecture.
Key risks
- kW-class thermal dissipation if fixed-rail linear output is required to operate continuously at full scale and 500 kHz.
- 220 VAC plus ±1000 V output creates severe safety, isolation, creepage, clearance, and enclosure requirements.
- HV arc, short, and cable capacitance can exceed nominal 1.5 nF load assumptions.
- HV feedback divider compensation is critical for flatness and stability.
- SiC MOSFET SOA must be validated; pulsed current rating alone is not sufficient.
- Output connector and cable must support both voltage and high reactive current.
Validation
Success criteria
- Schematic includes all functional blocks and internal protection paths.
- Every active device is selected and wired from datasheet-recommended circuits.
- 220 VAC input protection and isolation are implemented per safety best practices.
- Output-stage simulation verifies 1.5 nF load behavior, slew limiting, and 6 A current protection.
- ERC passes with zero unresolved violations or justified exceptions.
- Layout does not begin until schematic is reviewed.
Planned checks
- Mains-input protection and power budget review.
- Reactive-current and thermal budget review.
- Device datasheet review: MOSFET, driver, feedback, current sensing, AC/DC front end, PFC/HV power conversion, protection.
- SPICE / behavioral simulation of BTL output into 1.5 nF.
- Thermal and SOA estimate for selected output devices.
- ERC and DRC review before manufacturing export.
Release-facing notes
Expected deliverables
- Project specification
- Topology and power budget
- Datasheet-grounded schematic
- PCB layout after schematic approval
- BOM with MPN, manufacturer, and LCSC/JLCPCB fields where available
- Manufacturing package after review is clean
Special release notes
- Do not substitute HV, isolation, mains, or safety components without re-checking ratings and certifications.
- Keep external interfaces limited to 220 VAC power, signal input, and signal output unless explicitly revised.
Change notes / open questions
Changes in this revision
- Fixed power input is now explicitly 220 VAC only.
- External interfaces are strictly limited to power input, signal input, and signal output.
- Removed the previous external ±600 V / ±650 V supply prototype assumption.
- Latest requirement uses 1.5 nF load and 6 A overcurrent threshold.
- Selected first architecture direction: floating differential BTL fixed-HV-rail linear amplifier with internal mains-derived isolated HV/LV supplies.
- Added mandatory slew limit: ≤4000 V/µs.
Open questions
- Burst repetition rate / cooldown interval after a 10 ms full-scale 500 kHz burst?
- Floating differential output acceptable, or must output be ground-referenced?
- Required waveform fidelity: THD, phase error, flatness, overshoot, settling time?
- Load tolerance: cable capacitance, open load, short circuit, arc behavior?
- Current-limit behavior: clamp, foldback, latch-off, or hiccup?
- Cooling method and allowed heatsink/fan/enclosure size?
- Target safety standard: IEC 61010, IEC 62368, medical, lab equipment, or other?
See the topology and budget project file for detailed calculations and block-level architecture.
Design Summary
Scope
In scope
Out of scope for first schematic freeze
System context
Requirements
Functional
Electrical
Key constraints
Dependencies and risks
Dependencies
Key risks
Validation
Success criteria
Planned checks
Release-facing notes
Expected deliverables
Special release notes
Change notes / open questions
Changes in this revision
Open questions
