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Project Specification — Ozone Generator Control Board
Purpose
This project is a microcontroller-based control board for an ozone generator subsystem. The hardware appears intended to accept a DC input supply, generate regulated logic/sensor rails, monitor two analog pressure/flow channels, and switch up to three VIN-powered external loads such as an ozone module, fan, pump, solenoid, relay, or auxiliary actuator.
Documentation status
Created from the live schematic, BOM, PCB layout summary, and active design-review results on 2026-05-16. No prior project files were present.
Major functional requirements
Table
| Area | Requirement | Current implementation |
|---|---|---|
| DC input | Accept selectable 12 V or 24 V DC input through a 2-pin connector with input protection | J1 input, F1 resettable fuse, D1 TVS, D2 Schottky/reverse-protection path, bulk capacitance |
| Input/load current | Support roughly 3.5 A at 12 V or 1.8 A at 24 V; design high-current path with 5.25 A continuous-equivalent margin using 1.5x sizing | Current schematic topology supports VIN distribution, but F1 appears undersized for this envelope and must be re-rated/replaced |
| Power conversion | Generate intermediate rail and 3.3 V logic rail | U2 TPS54531 buck converter, U3 AMS1117-3.3 LDO |
| MCU control | Control outputs and read analog feedback | U1 ATMEGA328PB-AU with 16 MHz crystal and ICSP header |
| Load switching | Switch multiple VIN-powered loads using low-side MOSFETs | Q1/Q2/Q3 AO3400A; Q1 driven through U4 TC4427A gate driver |
| Sensor feedback | Read two pressure/flow sensors | U5/U6 Omron 2SMPP-03 sensors amplified by U7 INA2331AIPWT into MCU ADC inputs |
| Service/debug | Provide programming and communication access | J7 ICSP header, J5/J6 serial/control connectors |
| User status | Provide visual status indicators | LED1/LED2/LED3 and associated current-limit resistors |
Electrical architecture
Diagram
Connector map
Table
| Connector | Apparent role | Key connections | Notes |
|---|---|---|---|
| J1 | Main DC input | P1 raw input, P2 GND | Feeds F1 then D2 then VIN rail |
| J2 | Switched VIN load output 1 | P1 VIN, P2 Q1 drain/switch node | Field device must match selected VIN, either 12 V or 24 V; Q1 path has gate driver, flyback/clamp, and TVS; likely main/high-energy output |
| J3 | Switched VIN load output 2 | P1 VIN, P2 Q2 drain/switch node | Field device must match selected VIN, either 12 V or 24 V; Q2 gate driven by MCU through resistor and pulldown |
| J4 | Switched VIN load output 3 | P1 VIN, P2 Q3 drain/switch node | Q3 gate driven by MCU through resistor and pulldown |
| J5 | Serial/control connector | PD1, PD0, GND | Function labels not present; likely UART/control panel |
| J6 | 6-pin external interface | PB4, PD1, PD0, 3.3 V, GND, GND | Likely combined control/service interface |
| J7 | ICSP/programming header | 3.3 V, PB5, PB3, RESET, GND, plus Pin 1 | Pin mapping should be confirmed against intended AVR ISP standard |
Key ICs and active parts
Table
| Designator | Part | Function |
|---|---|---|
| U1 | ATMEGA328PB-AU | Main MCU |
| U2 | TPS54531DDA | Buck regulator, likely VIN to about 5 V |
| U3 | AMS1117-3.3 | 3.3 V regulator from buck output |
| U4 | TC4427AEOA | MOSFET gate driver for Q1 |
| U5, U6 | 2SMPP-03 | Pressure/flow sensors |
| U7 | INA2331AIPWT | Dual instrumentation amplifier for sensor outputs |
| Q1, Q2, Q3 | AO3400A | Low-side load switches |
Assumptions and open requirements
The schematic does not contain labels for all external loads or firmware thresholds. The following are now known:
- VIN is either 12 V DC or 24 V DC.
- Total input/load envelope is approximately 3.5 A at 12 V (42 W) or 1.8 A at 24 V (43.2 W).
- J1/J2/J3 connected devices are matched to the selected input voltage.
These items should still be confirmed before release:
- Actual current split between J2, J3, and J4.
- Whether J4 is also a VIN-matched field device.
- Whether J2 is the ozone high-voltage module output.
- Pressure/flow sensor mechanical connection and valid operating thresholds.
- LED meaning and desired fault/status behavior.
- UART/control connector protocol and pinout.
- Required safety interlocks, watchdog behavior, startup timing, and ozone-off fail-safe conditions.
Current validation status
The project has a populated schematic and 90 mm x 90 mm, 2-layer PCB layout. The active review still reports unresolved issues, primarily 101 airwires and one MCU power-source ERC warning on U1:VCC / Net 47. Manufacturing export should wait until routing and review remediation are complete.
Additional power-path blocker: F1 SMD1812B075TF/33 appears to be a 0.75 A-class resettable fuse and is not appropriate for the clarified 3.5 A at 12 V input envelope. Replace or re-rate F1 before manufacturing.
Purpose
Documentation status
Major functional requirements
Electrical architecture
Connector map
Key ICs and active parts
Assumptions and open requirements
Current validation status
