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Design Notes — Ozone Generator Control Board
Source basis
These notes were generated from the current schematic, BOM, layout, and review data. Several external connector functions are inferred from topology because the schematic uses mostly auto-generated net names and does not include connector labels.
Functional block breakdown
1. Input protection and VIN distribution
- J1 is the main two-pin DC input connector.
- VIN is clarified as selectable 12 V or 24 V DC.
- The input/load envelope is roughly 3.5 A at 12 V or 1.8 A at 24 V, which is about 42 W to 43.2 W.
- Use the 12 V / 3.5 A case for current sizing and the 24 V case for voltage-stress sizing.
- J1:P1 feeds F1, then D2, then the protected VIN rail.
- J1:P2 is ground.
- D1 is a TVS across the input-side rail to ground.
- C1/C2 and local ceramic capacitors provide bulk and high-frequency input energy storage.
- Protected VIN distributes to U2 and to load connectors J2, J3, and J4.
2. Power conversion
- U2 TPS54531DDA is configured as a buck regulator.
- The feedback divider R2 = 52.3 kΩ and R3 = 10 kΩ implies approximately 5.0 V output if the regulator reference is 0.8 V.
- U3 AMS1117-3.3 generates the 3.3 V logic/sensor rail from the buck output.
- Net 47 is the 3.3 V rail and powers U1, U5, U6, U7, J6 Pin 4, and J7 Pin 2.
- U1 AVCC is filtered from the 3.3 V rail through L2 and decoupled locally.
3. MCU and programming
- U1 ATMEGA328PB-AU is the main controller.
- Y1 with C7/C8 provides the external crystal/resonator network.
- Reset is on U1
RESET/PC6 with R1 pull-up and C17 reset capacitor network. - J7 is a 6-pin programming/service header tied to VCC, GND, RESET, PB3, and PB5. Confirm final pinout against the intended AVR ISP cable before fabrication.
4. Load switching
- J2, J3, and J4 appear to be VIN-powered load outputs.
- J2 and J3 field devices are now specified as voltage-matched to the selected VIN: use 12 V devices when VIN is 12 V and 24 V devices when VIN is 24 V.
- Each output has one side tied to VIN and the other side switched to ground through an AO3400A N-channel MOSFET.
- Q1 is driven through U4 TC4427AEOA, suggesting J2 is the highest-speed or highest-gate-charge/highest-energy output.
- Q2 is driven directly from U1 PB0 through R9 with R10 pulldown.
- Q3 is driven directly from U1 PD7 through R11 with R12 pulldown.
- D5/D6 provide clamp/flyback paths for Q1/Q2 switched outputs. Q1 also has D4 TVS and an RC snubber-like network.
5. Sensor signal chain
- U5 and U6 are Omron 2SMPP-03 pressure sensors.
- Sensor differential outputs feed U7 INA2331AIPWT.
- U7 channel A output goes to U1 PC0/ADC0.
- U7 channel B output goes to U1 PC1/ADC1.
- U7 reference pins are grounded, so the amplified output is referenced to ground.
- U7 shutdown pins are tied to 3.3 V, so both channels are enabled continuously.
6. User/status and communication I/O
- LED paths are present on PB2, PB3, and PB5-derived nets.
- PD0/PD1 route to J5 and J6 and are likely the UART RX/TX interface.
- J6 also carries PB4, 3.3 V, and ground; it may be an external control/display/service connector.
MCU pin map summary
Table
| MCU pin | Net | Connected items | Likely use |
|---|---|---|---|
| PD0 | Net 36 | J6 Pin 3, J5 Pin 2 | UART RX / serial signal |
| PD1 | Net 24 | J6 Pin 2, J5 Pin 1 | UART TX / serial signal |
| PD7 | Net 31 | R11 | Q3 load control |
| PB0 | Net 32 | R9 | Q2 load control |
| PB1 | Net 26 | U4 IN_A | Q1 gate-driver input |
| PB2 | Net 38 | R13 | LED/status output |
| PB3 | Net 19 | J7 Pin 4, R14 | SPI/programming MOSI and LED/status output |
| PB4 | Net 21 | J6 Pin 1 | External connector / possible SPI MISO |
| PB5 | Net 18 | J7 Pin 3, R5 | SPI/programming SCK and indicator path |
| PC0 | Net 13 | U7 VOUTA | Analog sensor A input |
| PC1 | Net 46 | U7 VOUTB | Analog sensor B input |
| PC6 / RESET | Net 20 | R1, C17, J7 Pin 5 | Reset |
| PB6 / XTAL1 | Net 39 | Y1, C7 | Crystal input |
| PB7 / XTAL2 | Net 15 | Y1, C8 | Crystal output |
| AREF | Net 16 | C16 | ADC reference decoupling |
| AVCC | Net 17 | L2, C15 | Filtered analog supply |
Layout observations
- Board is 90 mm x 90 mm, 2-layer, rectangular.
- All 70 physical BOM components are placed on the top layer.
- Component area is about 23.6% of board area, so placement density is low.
- Routing congestion is predicted near the MCU/sensor/header cluster around U1, C16, U7, J7, and J6.
- Current review reports 101 airwires, so routing is not complete.
Design risks and items to confirm
- F1 SMD1812B075TF/33 appears to be a 0.75 A-class PPTC and is undersized for the clarified 3.5 A input envelope; replace or re-rate it.
- D2 SS54-HF must be thermally checked at 3.5 A; diode dissipation may be high enough to justify an ideal-diode or P-channel MOSFET reverse-protection stage.
- Q1/Q2/Q3 AO3400A thermal dissipation must be checked at actual branch currents and actual gate-drive voltage. Q2/Q3 are MCU-driven and may be thermally marginal at sustained high current.
- Actual current split between J2/J3/J4 still needs confirmation.
- Whether the Q1/J2 output is intended for the ozone HV module.
- Whether J4 is also a VIN-matched field device and whether it is inductive; add clamp/flyback if inductive.
- Sensor pressure range, physical plumbing, and ADC threshold values.
- UART pinout and protocol for J5/J6.
- LED color/meaning and fault indication scheme.
- ERC warning: Net 47 powers U1 but is not recognized as driven by a power source; likely needs a power-net annotation or regulator output pin modeling fix.
- Complete routing and re-run DRC before fabrication.
Source basis
Functional block breakdown
1. Input protection and VIN distribution
2. Power conversion
3. MCU and programming
4. Load switching
5. Sensor signal chain
6. User/status and communication I/O
MCU pin map summary
Layout observations
Design risks and items to confirm
