Validation and Manufacturing Readiness — Ozone Generator Control Board
Snapshot
Generated on 2026-05-16 from the current schematic, PCB layout, BOM, and design review.
Current design state
Table
Area
Status
Notes
Schematic
Populated
152 schematic items, 48 nets
BOM
Populated
42 unique BOM parts, 70 BOM instances with MPNs present in summary
PCB board
Sized and placed
90 mm x 90 mm, 2-layer rectangular board, all BOM components on top side
Routing
Not complete
Review reports 101 airwires
Project files
Created
Specification, design notes, power budget, firmware starter, validation/manufacturing readiness
ERC
Not clean
One missing-power warning/error for U1:VCC on Net 47
DRC
Not clean
Airwires must be routed before manufacturing
VIN requirement
Partially defined
VIN is 12 V or 24 V DC; about 3.5 A at 12 V or 1.8 A at 24 V; J1/J2/J3 devices are matched to VIN
Active review issues
Blocking issues before fabrication
Table
Category
Count
Issue
Required action
DRC Airwires
101
Missing routed PCB traces
Route the PCB, then re-run review
ERC Missing Power
1
U1:VCC on Net 47 is not recognized as driven
Mark Net 47 as a power rail / fix power-source modeling from U3 output
Power path sizing
1
Existing F1 appears undersized for 12 V / 3.5 A input
Replace or re-rate F1 before manufacturing; size input path for at least 5.25 A continuous-equivalent margin
Documentation issue
The previous “project has no documentation” review issue should be resolved by the new project files created in this pass. Re-run review after the platform refreshes document indexing.
Manufacturing readiness gate
This board is not ready for manufacturing export yet.
Do not order PCBs or assembly until all of the following are true:
All airwires are routed.
ERC missing-power issue is resolved or explicitly justified.
Actual current split across J2/J3/J4 is confirmed; total envelope is now known as 3.5 A at 12 V or 1.8 A at 24 V.
Q1/Q2/Q3 thermal dissipation is checked against real load currents.
F1, D2, connectors, and VIN/load trace widths are verified for 3.5 A nominal and at least 5.25 A margin where full-current paths are possible.
If J4 load is inductive, a flyback/clamp protection path is added or documented as external.
J7 ICSP pinout is confirmed against the intended programming cable.
Sensor thresholds and firmware interlocks are calibrated and documented.
Final review shows no unresolved DRC/ERC errors.
Gerber, BOM, pick-and-place, and assembly notes are generated from the final reviewed revision.
Recommended next engineering actions
1. Clean up net names
Rename auto-numbered critical nets to explicit names before final review:
Table
Current net
Suggested name
Reason
Net 3
VIN_PROTECTED
Main protected input rail
Net 42
5V_BUCK
Buck output / LDO input
Net 47
3V3
Logic and sensor rail
Net 17
AVCC
Filtered MCU analog supply
Net 29
LOAD1_SW
J2/Q1 switched node
Net 14
LOAD2_SW
J3/Q2 switched node
Net 34
LOAD3_SW
J4/Q3 switched node
Net 13
PRESSURE_A_ADC
U7 channel A to MCU ADC
Net 46
PRESSURE_B_ADC
U7 channel B to MCU ADC
2. Resolve ERC power-source issue
Net 47 is generated by U3 AMS1117-3.3 output and powers U1 VCC, sensors, amplifier, and headers. The review reports U1:VCC as not driven. This is likely a modeling/annotation issue, not necessarily a wiring issue. Fix by ensuring the 3.3 V regulator output pin is treated as a power source and/or annotating Net 47 as a power net.
3. Route the board
The board has 101 airwires. After routing:
Re-run DRC.
Check high-current paths on VIN, J2, J3, and J4.
Verify ground return continuity and avoid thin return bottlenecks.
Keep analog sensor/amplifier traces away from switching-node and load-current traces.
4. Validate power and thermal margins
Before manufacturing, use the updated Power Budget file as the sizing basis:
VIN is 12 V / 3.5 A or 24 V / 1.8 A.
J1/J2/J3 field devices are voltage-matched to the selected VIN.
Input path target is at least 5.25 A continuous-equivalent margin using 1.5x sizing.
Actual current split between J2/J3/J4 still needs confirmation.
3.3 V load current from J6 if external hardware is powered.
Ambient temperature and enclosure airflow.
Copper weight.
Immediate power-path concern: F1 SMD1812B075TF/33 appears to be a 0.75 A-class resettable fuse and is not compatible with the clarified 3.5 A input envelope. D2 and Q1/Q2/Q3 also require thermal verification at the real branch currents.
5. Firmware bring-up validation
Use the Firmware Starter file as a bring-up scaffold:
First verify ADC readings with known pressure/flow conditions.
Keep Q1/J2 disabled until thresholds and safety interlocks are finalized.
Add watchdog, fault latch, and user command protocol before field use.
Pre-manufacturing checklist
Table
Check
Status
Schematic complete
Needs final review after load/function labels are confirmed
Datasheet-recommended circuits verified
Not fully verified in this documentation pass
Power budget complete
Updated with 12 V/3.5 A and 24 V/1.8 A envelope; still needs branch current split and thermal verification
PCB placement complete
Placed, but routing congestion near U1/U7/J7/J6 should be reviewed
PCB routing complete
No, 101 airwires remain
ERC clean
No, U1:VCC missing-power issue remains
DRC clean
No, airwires remain
BOM ready
Preliminary; verify availability and MPNs before purchase
Manufacturing files ready
No; wait until routing and reviews are clean
Final readiness conclusion
The project now has updated baseline documentation for the 12 V/24 V operating envelope, but the hardware is not manufacturing-ready. The next blocking work is to replace or re-rate F1, verify D2 and MOSFET thermals for the 3.5 A current case, resolve the U1:VCC ERC power-source issue, route the PCB, and re-run review until no unresolved critical issues remain.