Proceeding. The stopped run partially committed a substantial MPPT1 stage—four SiC MOSFETs, two 470 µH inductors, voltage/current sensors, protection, and interfaces are present—so I’ll preserve them and finish verification rather than rebuild.
MPPT1 is complete from the builder’s report. I’m doing an independent final read-back of the power-path inventory and ERC findings before accepting it as the reference channel.
MPPT1 reference stage is complete and independently verified: four IMZA75R040M2H SiC MOSFETs, two 470 µH phases, isolated voltage sensing, dual phase-current sensing, hardware overcurrent protection, gate interfaces, and DNP snubbers. Final schematic inventory is 212 components / 108 nets.
Open items
ERC only reports 18 duplicated UCC14141 output-power warnings and the intentional external HV_DC_LINK_PRECHARGE interface.
Inductor magnetics, snubbers, and gate resistors require thermal and double-pulse validation.
Recommended per-channel topology: a two-phase interleaved synchronous boost MPPT, not a full four-switch buck-boost, feeding a regulated nominal 450 V DC link.
The selected Canadian Solar arrays operate well below the 430–450 V DC link:
7S2P: 215.6 Vmp at STC and approximately 307.2 V preliminary cold Voc.
6S2P: 184.8 Vmp at STC and approximately 148.8 V estimated Vmp at a 75 °C cell temperature.
Because the PV maximum-power voltage does not cross above the DC link, a buck operating mode is unnecessary. A four-switch buck-boost would add two active switches per phase, isolated gate-drive channels, conduction loss, switching loss, fault paths, control transitions, and cost without improving operation for the selected strings.
If future requirements demand PV operation above the DC-link voltage, retain the same digital-control architecture but redesign the power cell as a two-phase interleaved four-switch non-inverting buck-boost. That is not recommended for the present hardware baseline.
Important Rating Reconciliation
The three stated ratings cannot apply simultaneously over the entire input range:
Text
Maximum input power from the 35 A current limit = Vin × 35 A
Full 6.5 kW requires Vin ≥ 6500 W / 35 A = 185.7 V
Therefore, the required operating envelope is:
Text
Pavailable(Vin) = min(6.5 kW, 35 A × Vin)
Table
PV input voltage
Maximum power under 35 A limit
130 V
4.55 kW
148.8 V estimated 6S hot Vmp
5.21 kW
184.8 V 6S STC Vmp
6.47 kW
185.7 V and above
6.5 kW capped
215.6 V 7S STC Vmp
6.5 kW capped
425 V
6.5 kW capped
This derating is acceptable for the selected arrays:
The 6S2P array is rated 4.8 kW at STC, below the 35 A envelope at 184.8 V.
At the estimated 148.8 V hot operating point, its available irradiance/power will normally be temperature-derated, and the converter can process up to approximately 5.21 kW under the 35 A limit.
The 7S2P arrays are 5.6 kW each and remain below the 6.5 kW converter rating.
The specification should describe 6.5 kW maximum power with a 35 A input-current limit, not 6.5 kW at every voltage down to 130 V.
Recommended Power Cell
Each MPPT channel should contain two identical boost phases operating 180 degrees apart:
Text
PV+ -> input protection/filter -> L1 -> switching node 1 -> synchronous boost half bridge --+
+--> 450 V DC link
PV+ -> input protection/filter -> L2 -> switching node 2 -> synchronous boost half bridge --+
PV- and DC-link negative share the transformerless power reference.
A synchronous boost phase uses:
One low-side controlled switch that stores energy in the inductor.
One high-side synchronous switch replacing the boost diode.
One dedicated boost inductor.
Local high-frequency film/ceramic commutation capacitance.
Per-phase current sensing.
Isolated high-side/low-side gate drive or an equivalent reinforced-isolation driver arrangement.
Synchronous operation is preferred over a diode boost at this power because it reduces high-current diode conduction loss and provides controlled discharge/reverse-current blocking behavior. Firmware and hardware must prevent reverse energy flow into a disabled or faulted PV string.
Preliminary Electrical Ratings per Channel
Table
Parameter
Recommended design value
MPPT tracking range
130–425 VDC
Startup threshold
≤120 VDC
Normal DC-link target
450 VDC nominal
PV absolute maximum
500 VDC system limit
Continuous input-current limit
35 A
Permitted input short-circuit rating
≥45 A
Maximum processed power
6.5 kW
Short-duration/clipping-safe input
7.0 kW
Full-power minimum input voltage
185.7 V
Number of interleaved phases
2
Phase displacement
180 degrees
Preliminary switching frequency
40–60 kHz per phase; use 50 kHz for first-pass magnetics
Target full-load efficiency
≥98% power-stage target, subject to verified loss model
The output stage must tolerate inverter/battery-driven DC-link transients. Use a separate bus-level overvoltage shutdown and energy-management strategy rather than assuming the MPPT can always regulate the bus.
Semiconductor Class
Use 750 V-class SiC MOSFETs for both controlled devices in each synchronous boost half bridge.
Rationale:
The nominal bus is 450 V.
The PV input has a 500 V absolute system limit.
650 V devices provide limited margin for commutation overshoot and abnormal bus events.
750 V devices offer a more appropriate transient margin while retaining substantially lower switching loss than 1200 V devices for this bus class.
Final device selection requires a loss model using:
RDS(on) at maximum junction temperature, not only 25 °C.
Switching energy at the actual bus voltage, gate resistance, and phase current.
Reverse-conduction and dead-time loss.
Output-capacitance energy and hard/soft commutation behavior.
Short-circuit withstand and gate-driver protection.
Package inductance, creepage, thermal interface, and cooling method.
Parallel MOSFETs should not be assumed necessary until the loss/thermal model is complete. A single suitably rated device per switch position may be practical at approximately 17.5 A maximum average phase current.
Preliminary Magnetics
At 450 V output and 50 kHz per phase, with total input current limited to 35 A:
Average current per phase: 17.5 A.
Target phase ripple: approximately 25%, or 4.38 A peak-to-peak.
Preliminary phase peak current: approximately 19.7 A before transient/overload margin.
Using the ideal boost estimate:
Text
D = 1 − Vin / 450
L = Vin × D / (ΔIL × fsw)
The worst first-pass calculated inductance is approximately 514 µH per phase near 216 V input. A provisional 470–560 µH per phase design range is therefore appropriate for detailed magnetic optimization.
Minimum preliminary inductor requirements:
Saturation current: at least 25 A at maximum core temperature; higher margin preferred.
RMS current: at least 20 A continuous after enclosure-temperature derating.
Low enough DCR to keep copper loss and thermal rise acceptable.
Core material validated for 50 kHz, DC bias, ripple flux, fringing, and worst-case ambient.
Insulation system and winding spacing appropriate for the PV/DC-link voltage and applicable standards.
This is not a final inductor value. Frequency, allowed ripple, core size, copper construction, thermal limits, and control bandwidth must be optimized together.
Input and Output Capacitors
PV-side input capacitance
The PV-side capacitor bank must:
Absorb interleaved switching ripple without destabilizing the PV-voltage control loop.
Remain small enough that MPPT voltage steps are observable and controllable.
Withstand 500 V plus required derating.
Use film capacitors for ripple current and life; use small high-voltage ceramics only for local high-frequency decoupling after DC-bias review.
Include discharge monitoring and a controlled safe-discharge path.
DC-link-side local capacitance
Each channel should have local high-frequency film capacitance close to the synchronous half bridges. The main 450 V bus capacitor bank is shared at system level and must be sized for inverter transients and 120 Hz ripple; it must not be duplicated blindly on every MPPT board.
Capacitor values require switching-ripple, control-loop, bus-impedance, and lifetime calculations.
Control Architecture
Use a digital real-time controller such as a C2000-class MCU or XMC7000-class MCU. One system controller can coordinate all three MPPT channels if it has sufficient synchronized PWM, ADC, comparator, trip, and CPU resources.
Recommended loops per channel:
Inner phase-current loops or average-current loop with active current balancing.
Outer PV-voltage loop commanding total input current.
MPPT supervisor using incremental conductance or perturb-and-observe at a much slower update rate.
Power/current limiter enforcing P ≤ min(6.5 kW, 35 A × Vin).
DC-link feedforward/limit logic that reduces PV power when the inverter and battery cannot absorb it.
The two phases should have independent current sensing so current imbalance, a saturated inductor, or a failed switch is detectable. Do not rely only on one combined current sensor.
Operating Modes
Startup
Verify polarity and insulation state.
Measure PV open-circuit voltage.
Keep both boost switches disabled while the DC link is pre-charged by the system-level pre-charge path.
Enable switching only when PV is above 120 V, the bus is in a controllable range, and no fault is active.
Ramp current reference gradually before enabling MPPT perturbations.
Normal MPPT boost
Operate both phases 180 degrees apart.
Regulate PV voltage to the MPPT reference.
Enforce 35 A total input current and 6.5 kW channel-power limits.
Apply active current sharing.
Near-pass-through region
At 425 V input and 450 V output, ideal boost duty is approximately 5.6%. Minimum on-time, dead time, current sampling, and pulse-skipping behavior become important. The controller should provide a stable low-duty mode or controlled bypass/pass-through strategy without allowing uncontrolled PV-to-bus current.
A full four-switch buck-boost would make crossover control easier if the input could exceed the bus, but that condition does not occur with the selected strings.
Shutdown and faults
Command zero current before disabling PWM when possible.
Block reverse bus-to-PV current.
Trip gate drives through hardware on phase overcurrent, bus overvoltage, driver fault, and severe current imbalance.
Open the channel disconnect/contactor when required by the fault classification.
Protection Requirements
Per channel:
500 V-rated PV disconnect and fusing arrangement.
Reverse-polarity detection before switching is enabled.
PV input-voltage sensing with independent overvoltage comparator.
Hardware bus-overvoltage trip below semiconductor and capacitor limits.
Per-phase cycle-by-cycle current limit.
Fast short-circuit/gate-driver fault shutdown.
Inductor-temperature and switch-temperature monitoring.
Input insulation/ground-fault coordination with the system insulation monitor.
Arc-fault and rapid-shutdown interfaces as required by the installation.
Pre-charge/discharge state verification.
Contactor/disconnect feedback and weld detection where contactors are used.
A preliminary current-trip hierarchy could use:
35 A commanded total operating limit.
Approximately 40 A controlled overload/soft limit.
Hardware phase trip chosen from the final ripple, sensor tolerance, saturation current, and semiconductor safe operating area.
Do not set the hardware trip directly from the 45 A array short-circuit rating; phase-current peak and fault dynamics must be calculated first.
Reference-Design Findings
Infineon REF-9KW2LBOOST
Two-channel interleaved two-level boost.
9 kW headline rating, 4.5 kW per channel.
24 kHz switching.
650 V CoolMOS plus 650 V SiC diode.
XMC7200 control and hardware current/voltage/temperature protection.
Useful architectural reference, but published testing did not validate the full headline power.
Three-phase interleaved boost with 120-degree phase displacement.
15 kW total, 5 kW per phase.
24 kHz switching.
1200 V IGBT plus 1200 V SiC diode for a much higher 750–850 V bus.
Reports approximately 98.7–98.8% semiconductor-stage efficiency at high load.
Strong reference for digital MPPT, phase interleaving, current sensing, gate-kill, and fault architecture, but its voltage/device class is higher than required here.
If an explicit contractual requirement demands 130–425 V input independent of a variable DC link that could fall below the PV voltage, use a two-phase interleaved four-switch non-inverting buck-boost:
Two complete four-switch cells, 180 degrees interleaved.
Eight 750 V SiC MOSFETs total per MPPT channel.
One inductor per cell.
Boost mode when PV is below the bus.
Buck mode when PV is above the bus.
Four-switch transition band around crossover.
This option should be selected only after defining the minimum DC-link voltage. If the bus is always maintained at 430–450 V, the extra buck leg is not justified.
Recommended Next Design Inputs
Before a detailed schematic and component selection:
Fix nominal/minimum/maximum DC-link voltage, including ride-through and transient limits.
Define switching-frequency target from acoustic, magnetic, EMI, and efficiency constraints.
Define ambient/coolant temperature and cooling method.
Define allowable inductor ripple and MPPT voltage ripple.
Define required efficiency and power-density targets.
Define bus-capacitor architecture and allowable MPPT contribution to 120 Hz ripple.
Decide whether one controller manages all three channels or each channel has an independent controller.
Complete semiconductor loss, magnetic loss, capacitor ripple/lifetime, control-loop, and fault-energy simulations.
Final Recommendation
Proceed with a two-phase interleaved synchronous boost MPPT channel using 750 V SiC devices, a 450 V nominal DC link, 50 kHz preliminary switching frequency, and approximately 470–560 µH per-phase inductors. Implement 6.5 kW as a power ceiling with a 35 A input-current ceiling, giving full power only above 185.7 V.
Do not use a full four-switch buck-boost unless the DC link is later allowed to fall below the PV operating voltage or future PV strings can operate above the bus.