I’m blocked because your account has no available ACUs, so I can’t run any more layout or DRC cleanup tools right now.
Accomplished:
Applied a 6-layer stackup attempt and an explicit 6-layer stackup definition.
Cleared stale partial routing.
Spread the U1/U2/U6 cluster and support passives for better BGA escape.
Re-ran the router; it applied 884 routing nodes.
USB signal-integrity checks queried for USB returned no matching issues, but final DRC is not clean.
Open items:
Final DRC still shows 33 airwire errors.
Final DRC also shows 67 invalid Smart Via layer errors, indicating the same stackup recognition issue remains: stackup inspection shows the new stackup name, but layout summary still reports 2 copper layers.
Some USB1 routing airwires remain in the final DRC list.
Suggested next steps when ACUs are available:
Resolve the stackup/copper-layer recognition issue first.
Delete or remap invalid Smart Vias after the stackup is recognized correctly.
Surgically route the remaining USB1, MCU power, UART, FlexSPI, and debug airwires.
Run final DRC again before treating the PCB as manufacturing-ready.