The builder completed the risk-reduction changes and documentation. I’m doing the required independent read-only review now; after that we are at the schematic-completion checkpoint, with visual schematic cleanup as the only known unfinished item before layout.
The Phase 1 schematic and engineering package were substantially completed:
Expanded to 78 components and 42 nets
Added independent battery-temperature telemetry
Corrected the bulk capacitor, regulator inductor, and motor-connector selections
Selected low-cost JYC1027 ERM motors
Updated the power budget, BLE protocol, BOM, firmware starter, and bring-up plan
Added wireless compliance, safety-analysis, and preliminary FMEA files
Builder checks reported no electrical, passive, system, or schematic-legibility errors or warnings
The independent review executor finished, but I could not retrieve and reconcile its final findings. The schematic also remains visually crowded; electrical connectivity is complete, but functional-block organization still needs improvement before PCB layout.
We are effectively at the schematic-completion checkpoint, pending:
Reconcile the independent review findings
Apply any required corrections
Clean up the schematic canvas
Obtain your approval before PCB placement and routing
This budget is tied to the live 78-component, 42-net schematic after risk remediation.
The TPS63031 provides 3.3 V across the useful LiPo range. At 3.0 V input and 3.3 V output, measured datasheet efficiency is 84% at 10 mA and 86% at 100 mA with power-save enabled; the same curve reports 75% at 500 mA. Its typical-characteristics output-current capability is 680 mA at 3.0 V input and 3.3 V output. PS/SYNC is tied low in the schematic, which enables power-save mode.
Rails and loads
Table
Rail
Loads
Budget basis
DOCK_5V_RAW
J1 to D1
5 V dock input, 500 mA design limit
DOCK_5V_PROTECTED
D1, D2, C1, IC1 IN, TP1
Reverse-polarity Schottky plus ESD protection
BAT_PROTECTED
J2, IC1 BAT, J3–J6 motors, C13/C14, ADC divider
1S protected LiPo, 3.0–4.2 V useful range
SYS_OUT
IC1 OUT, U2 input, C2, TP3
Logic power-path node; schematic metadata limit 0.8 A
3V3
U3, U4/U5, LED1, status pull-ups, J7 VTref
Regulated logic rail; schematic metadata limit 0.5 A
U3 radio TX at 0 dBm is 4.8 mA typical using DC/DC from 3 V; 1 Mbps BLE RX is 4.6 mA typical using DC/DC from 3 V.
U3 System ON idle is 1.5 µA at 3 V with no RAM retention and RTC wake; System OFF is 0.4 µA with no RAM retention.
Each STTS22H averages 1.75 µA in one-shot mode at one sample per second; 1 Hz low-ODR operation is 2.0 µA typical, while an active conversion is 120 µA typical/180 µA maximum.
The RGB LED is firmware duty-limited. Its datasheet allows 20 mA steady per die, but the fitted R19/R20/R21 values intentionally use much lower practical currents.
ERM assumptions
The prototype sourcing target is Jie Yi JYC1027, a 10 mm nominal-3 V coin ERM. Published distributor data gives an 80 mA rated-current ceiling for this class; until incoming-lot measurements are complete, the existing 80 mA running and 120 mA startup allowances remain the electrical design basis.
Nominal motor voltage: 3.0 V.
Running current: 80 mA per motor at 3 V.
Startup/stall design allowance: 120 mA per motor.
Firmware normally enables only one motor at a time.
Representative shift profile: one motor has 50% aggregate on-time across guidance periods. This is intentionally conservative for runtime planning.
Above 3.0 V battery voltage, firmware limits effective motor voltage by PWM. Initial ceiling: duty min(100%, 3.0 V / measured battery voltage) before intensity scaling.
Q1–Q4 are AO3400A devices. Their datasheet gives 5.7 A continuous drain-current rating at 25 °C, far above the assumed motor surge; final thermal performance still depends on the PCB copper and SOT-23 conditions.
Operating-state budget
Table
State
3V3 load model
Direct motor load
Estimated battery current
Deep sleep
MCU RTC wake, sensors quiescent, divider and regulator quiescent allowance
0
0.08 mA
BLE idle/advertising
Low duty radio and firmware housekeeping
0
2.0 mA
BLE active, no motor
Conservative 8 mA on 3V3 reflected through U2 at depleted-cell efficiency plus margin
0
10.2 mA
Representative haptic
Active BLE/electronics
80 mA × 50%
50.2 mA average
One-motor electrical peak
Active electronics transient allowance
120 mA
135 mA peak
Accidental four-motor peak
Active electronics transient allowance
4 × 120 mA
495 mA peak
At depleted LiPo, the 3V3 input-current reflection is calculated with the lowest useful cell voltage, not nominal voltage. The representative and motor-peak figures include conservative margin rather than claiming a precision prediction before motor and firmware measurements exist.
Runtime
A practical 80% usable-capacity factor is applied for cell protection cutoff, aging, temperature, conversion loss uncertainty, and capacity tolerance.
Table
Cell
Usable capacity
Sleep
BLE idle
BLE active/no motor
Representative haptic
500 mAh
400 mAh
5000 h
200 h
39.2 h
8.0 h
650 mAh
520 mAh
6500 h
260 h
51.0 h
10.4 h
800 mAh
640 mAh
8000 h
320 h
62.7 h
12.7 h
Peak-state runtimes are not intended use cases: continuously holding one assumed motor peak would give about 3.0/3.9/4.7 h for 500/650/800 mAh, and a continuous four-motor fault would give only about 0.81/1.05/1.29 h. Firmware must prevent both.
Battery recommendation
Recommend a protected 650 mAh 1S LiPo as the Phase 1 default, with a continuous discharge rating of at least 1 A, verified connector polarity, and both TH1 and TH2 thermally bonded to the cell. TH1 remains dedicated to autonomous charger safety; TH2 provides MCU telemetry.
Charger and path verification
R1 = 3.0 kΩ gives approximately 297 mA from the BQ24074 ISET constant of 890 AΩ.
R2 = 3.1 kΩ gives 500 mA input limit using RILIM = KILIM / II_MAX, with KILIM = 1550 AΩ.
R3 = 3.0 kΩ programs an approximately 30 mA termination target per the schematic design intent; confirm on hardware because the ITERM equation extraction was not independently machine-verified.
R4 = 46.4 kΩ is intended for a nominal 6.25-hour fast-charge safety timer. The BQ24074 uses a TMR-to-ground resistor and defines the fast-charge timer as 10 × KTMR × RTMR; confirm the measured timeout rather than relying only on nominal tolerance.
The BQ24074 gives the system load priority and reduces charge current in DPPM when load plus charging exceeds the input limit; the battery can supplement the system load after charge current reaches zero.
The charger TS function is designed for a 10 kΩ NTC and nominal 0–50 °C charge window with 3 °C trip hysteresis.
At a 500 mA dock limit, a 297 mA charge leaves about 203 mA for the system before DPPM reduces charging. The normal logic load is far below that. Motors are on BAT_PROTECTED, so docked motor operation can still draw from the battery; firmware policy must suppress haptics while docked except a bounded service self-test.
Path and transient margins
BAT_PROTECTED schematic current metadata is 1.2 A, exceeding the 495 mA accidental peak by 2.4×.
J2 is rated as a 2 A-class JST-PH connection in the selected library data, providing useful prototype margin.
C13 is now a real polarized KEMET T491C227K010AT, 220 µF, 10 V, case C part rather than an impossible 0603 assignment. C13 and C14 reduce edge noise but do not supply a four-motor event by themselves: ideal 220 µF droop is about 2.18 V for 480 mA over 1 ms; the protected cell, wiring, connector, and copper carry the surge.
L3 is now Bourns SRP2010-1R5M, 1.5 µH shielded. TPS63031 specifies 1.5 µH in the 3.3 V application and requires the inductor saturation-current rating to exceed calculated maximum inductor current by 20%.
TH2/R23/C16 are excited only during a reading by U3 P0.29. Therefore the 10 kΩ/10 kΩ divider does not impose a continuous ~165 µA 3V3 load; runtime figures remain effectively unchanged at the stated precision.
U2's cited 680 mA typical output capability at 3.0 V input exceeds the estimated electronics-only peak by a wide margin, but motors must remain off the 3V3 rail.
Validation measurements required
Measure each selected motor running, startup, and hard-stall current at 3.0, 3.7, and 4.2 V with PWM limiting.
Log representative firmware duty cycle during a full protocol session.
Measure sleep, advertising, connected-idle, active BLE, LED, and sensor currents at the battery connector.
Repeat runtime test at room temperature and the lowest intended use temperature.
Verify protected-cell cutoff does not nuisance-trip during four-channel fault injection.
Verify charging current and TS trip behavior on the assembled PCB.
Open risks
JYC1027 is the prototype sourcing target, but motor attachment, lead length, and wrist mechanical stack still require sample validation; measure each incoming lot.
C13 is polarized tantalum: verify surge behavior and assembly polarity, and reassess polymer/MLCC alternatives if motor transients or drop testing show excessive stress.
SRP2010-1R5M selection must be validated against measured peak inductor current and temperature; the TPS63031 requirement is calculation-based, not a universal numeric current rating.