# [2-layer] JLCPCB Constraints eX19 ## Description Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules ## Project Details - **Owner:** pravinbro - **Created:** 11/24/2024 - **Last Updated:** 11/24/2024 - **Visibility:** Public ## Key Components ### U1 — [ESP32-C3-MINI-1-N4](https://www.flux.ai/jecstronic/esp32-c3-mini-1-n4~wbz.md) - License: https://creativecommons.org/licenses/by/4.0/ - Datasheet URL: https://www.espressif.com/sites/default/files/documentation/esp32-c3-mini-1_datasheet_en.pdf - Manufacturer Part Number: ESP32-C3-MINI-1-N4 - Manufacturer Name: Espressif Systems - Part Type: Module **Pins:** - 3V3 [pin 3] - EN [pin 8] - GND [pin 51] - GND [pin 36] - GND [pin 49_9] - GND [pin 1] - GND [pin 49_6] - GND [pin 46] - GND [pin 49_3] - GND [pin 43] - GND [pin 49_7] - GND [pin 39] - GND [pin 14] - GND [pin 41] - GND [pin 37] - GND [pin 53] - GND [pin 42] - GND [pin 49_2] - GND [pin 49_1] - GND [pin 45] - GND [pin 11] - GND [pin 38] - GND [pin 52] - GND [pin 2] - GND [pin 48] - GND [pin 49_4] - GND [pin 40] - GND [pin 49_5] - GND [pin 49_8] - GND [pin 44] - GND [pin 47] - GND [pin 50] - IO0 [pin 12] - IO1 [pin 13] - IO10 [pin 16] - IO18 [pin 26] - IO19 [pin 27] - IO2 [pin 5] - IO3 [pin 6] - IO4 [pin 18] - IO5 [pin 19] - IO6 [pin 20] - IO7 [pin 21] - IO8 [pin 22] - IO9 [pin 23] - NC [pin 35] - NC [pin 4] - NC [pin 10] - NC [pin 32] - NC [pin 7] - NC [pin 9] - NC [pin 28] - NC [pin 24] - NC [pin 15] - NC [pin 34] - NC [pin 29] - NC [pin 17] - NC [pin 33] - NC [pin 25] - RXD0 [pin 30] - TXD0 [pin 31] *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/pravinbro/2-layer-jlcpcb-constraints-ex19~52](https://www.flux.ai/pravinbro/2-layer-jlcpcb-constraints-ex19~52).* --- *Generated from [https://www.flux.ai/pravinbro/2-layer-jlcpcb-constraints-ex19~52](https://www.flux.ai/pravinbro/2-layer-jlcpcb-constraints-ex19~52)*