Blinking LED Circuit Design
Thought
Work done
- Audite9 el esqueme1tico y el estado del PCB: confirme9 el stackup de 4 capas, el tamaf1o actual de 160 d7 100 mm, y la distribucif3n general de los bloques de potencia, sensado y ESP32.
- Revise9 la documentacif3n del proyecto y verifique9 que el frente analf3gico usa ADC1 del ESP32 y que sigue pendiente la separacif3n segura entre red y SELV en PCB.
- Identifique9 los problemas esqueme1ticos principales que siguen abiertos: la referencia del canal CT quedf3 como una red mal nombrada, y el ERC de U1:VIN sigue reportando Missing Power.
- Intente9 reconstruir y nombrar la red de bias del CT, pero la verificacif3n final mostrf3 que afan aparece como una segunda red GND en lugar de una etiqueta clara tipo CT_BIAS.
Success criteria review
- 274c Todas las conexiones del esqueme1tico este1n en regla, sin advertencias ERC/DRC pendientes.
- 274c El esqueme1tico incluye toda la documentacif3n y etiquetas completadas.
- 274c La PCB presenta separacif3n SELV/red, placement y routing listos para revisif3n.
- 274c El proyecto queda listo para revisif3n final y fabricacif3n.
Next steps
Queda por resolver la red de referencia del CT para que no aparezca como GND, eliminar correctamente el ERC residual de U1:VIN, y luego continuar con la preparacif3n de PCB: dimensionado definitivo, reglas de seguridad mains/SELV, placement autome1tico por zonas y auto-routing. En cuanto pueda continuar la ejecucif3n, sigo desde ese punto.
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Design Notes
Architecture Overview
- AC line under measurement feeds two sensing paths:
- Current path through external SCT-013 current transformer and burden/filter network into an ESP32 ADC input.
- Voltage path through ZMPT101B voltage transformer front-end and scaling/filter network into a second ESP32 ADC input.
- Control and communications are handled by an ESP32 DevKit module to simplify WiFi connectivity, firmware bring-up, and power integration.
- Primary power comes from HLK-PM01 AC-DC module, generating 5 V from mains. A secondary regulator stage generates the 3.3 V logic rail for the ESP32 and analog front-end.
- Protection includes line fuse, MOV, input NTC (optional inrush limiting), diode clamps on analog inputs, and opto-isolation support using PC817 where digital/event isolation is beneficial.
- Basic user interface includes one status LED and one pushbutton used for reset/config or boot interaction.
Initial Engineering Decisions
- Use an ESP32 module/dev board instead of a bare ESP32 chip to reduce RF risk and accelerate prototyping.
- Use ADC1-capable ESP32 pins for analog sensing so WiFi operation does not conflict with ADC2 limitations.
- Keep the mains-derived power and sensing circuitry separated from the low-voltage logic domain; preserve clear net naming for future PCB zoning.
- Add RC low-pass filtering at each ADC input to reduce aliasing/noise before digital signal processing.
- Use generic passives for resistors/capacitors during schematic capture; finalize exact production MPNs in the physical-constraints stage.
Planned Signal Assignment
- ADC current channel: ESP32 ADC1 input (preferred GPIO34/35/36/39 depending module pin exposure)
- ADC voltage channel: ESP32 ADC1 input (different ADC1 channel from current)
- Status LED: one digital output GPIO
- Config/boot button: one GPIO with pull-up/down strategy consistent with ESP32 boot rules
Safety Notes
- This design touches mains-referenced circuitry. Maintain galvanic isolation where intended by the transformer-based sensing path and AC-DC module.
- PCB stage must enforce creepage/clearance between hazardous-voltage nets and SELV nets.
- HLK-PM01, MOV, fuse, and any optional NTC belong to the hazardous-voltage entry section and must remain physically isolated in layout.
Architecture Overview
Initial Engineering Decisions
Planned Signal Assignment
Safety Notes
